placing addiional caps across existing caps to reduce noise

I will be doing that when I am ready to layout my next board.

Reply to
rickman
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The amount of decoupling required is not a function of the clock rate. It depends on the slew rate of your signals and the length of the transmission lines. The length determines the lower frequencies you will need to decouple and the slew rate determines the highest frequencies. Of course there are other aspects that you need to decouple, such as switching inside the chips. For that you need to compare the maximum transition in current the chip will produce to the maximum noise voltage you can tolerate. Then use the resulting impedance as the goal for decoupling.

Ritchey's data was very clear on this. Adding a single value of caps to a power plane produced a resonance with a higher impedance than that of the plane alone over a significant frequency range. By using multiple cap values he was able to decouple a board with just a handfull of caps rather than the mountain that are normally used. Most importantly, he could show that his decoupling design worked correctly before he built the board rather than verifying it in testing.

I wish I could post the images from Ritchey's book. I have tried to describe his measurements in detail, but a picture is worth a thousand words (or maybe more). Moving the SRF is what makes it work. If you use a hundred 0.1 uF caps you should get a parallel resonant peak in impedance as the capacitor resonates with the power plane. Assuming the capacitor has a high Q, then no number of capacitors will significantly reduce that peak. Of course the caps don't have a high Q so some number of caps *will* reduce the peak to an acceptable level. Or you can add a smaller number of caps with a smaller value. These caps will produce a higher frequency resonance with the power plane. You can then add a third value of cap to move that resonance higher. Each time you add a value of cap you flatten the impedance curve. If the caps are not high Q, by the time you have added 0.1, 0.01 and 0.001 caps you will have flattened it enough to not see any real peaks, but rather just ripple in the frequency response. This will take a lot fewer caps than the hundreds that are often used on boards, even at the frequencies you are using.

Or think of it from the other direction. You add the 0.001 uF caps to decouple the plane at the highest frequencies that caps can be effective. But they don't work well at lower frequencies so add a smaller number of 0.01 uF caps to provide decoupling at a lower frequency. Then add just a small number of 0.1 uF caps for the lower freqs and so on down to the tantalum caps for bulk at the lowest frequencies until the PSU response time can adequately maintain the voltage.

Reply to
rickman

Thanks for taking the time explaining this - between you and Symon I'm hopefully learning something!

However, I've a couple of issues here. First off, I can't see that the power planes have much capacitive effect at these frequencies (the "planes" being polygons, with other signals on the same layer, and thus having plenty of gaps). But I'll happily admit to not having a clear idea how to model such planes or polygons.

Secondly, I understand about different caps working better at different frequencies, and obviously have bulk capacitors for the lower frequencies (electrolytics near the regulators, and a few 4.7uF ceramics around the board). But I still can't find any reason to expect a 0.001 uF ceramic 0603 capacitor to be significantly better at higher frequencies than a 0.1 uF ceramic (same dialectric) 0603 capacitor.

Using the muRata software, I picked a 0603 X7R 100 nF capacitor. The software gives it an SRF of 21 MHz, L of 0.63 nH, R of 0.027 O, and an impedance of 0.14 ohm at 10 MHz, 0.02 ohm at 20 MHz, 0.16 ohm at 50 MHz,

0.38 ohm at 100 MHz, 0.78 at 200 MHz, and 1.97 ohm at 500 MHz. Picking a 10 nF cap with the same setup gives an SFR of 67 MHz, and impedances at these frequencies of 1.66, 0.77, 0.16, 0.24, 0.71 and 1.95 ohms. In other words, it is a better at around 100 MHz, but not vastly better. Until we start looking at special 0306 caps for frequencies of several hundred MHz, I just don't see the benefit of smaller capacitance values. Even then, it is more economical to simply use a few extra caps of the same type (assuming the board has space for it).

It doesn't even take that many caps - I've got about a dozen for the processor (which as two main supplies and a PLL supply), two or three for each of the sdram chips, and one or two for each of the other major chips.

One thing that makes a significant difference is that I'm not driving any fast, high current lines - signalling is (almost) all TTL levels. Higher current drives would mean more capacitors, but I'd still expect to use the same types.

Reply to
David Brown

effect

Rick, OK, I think you're correct, this conversation has reached an end. It can go nowhere with one of us posting data and sims (including ones that model the power planes, albeit as a lumped capacitance) that the other cannot or will not look at, the other posting hearsay from a class he went to. I will, however, try to make one last point based on the snippet above.

I contend that the package impedance of modern FPGAs is such that any benefit that a board wide power plane's capacitance could provide to your design, over and above that which you can get from a small local plane and associated bypass capacitors, is negligible. The caps work up to a few hundred MHz, just about where the package stops working. Any noise on the supply above this frequency doesn't get to the silicon anyway. As posting a simulation to show this is wasted effort, I instead refer you to UG076, Figure 6-3, which shows how Xilinx power their Rocket-IO circuitry. I also offer

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as further reading.

Thanks for encouraging me to simulate this stuff again, it's given me some more ideas for my next layout! I'm also gladdened that, as you mention in one of your posts, you will be simulating your next board. If you are able to share your results, I for one would be most interested to see them. Yours &c, Syms.

Reply to
Symon

I had written a reply to this post, but I hit a wrong button as I typed and POOF! So here it is again...

If your planes are not designed to have good capacitance, then they won't. They need to be complete on thier own layer and closely spaced. It is not hard to get nFs from planes with very low inductance.

It is not just that the caps work at different frequencies, it is how they work with the power planes. A cap closely coupled to the power planes will have a resonance (or anti-resonance) which will create a

*higher* impedance in that range of frequencies than either the cap or plane alone. If you pick a cap of small value and low Q (high ESR) it will have a low amplitude resonance, high in frequency. This same cap will require a lot of them to provide effective coupling at lower frequencies. So you can then use a smaller number of larger value caps to provide a lowered impedance at lower frequencies. Again it is important to not use parts with a high Q as this will raise the amplitude of the impedance peaks due to parallel resonance. By using a range of cap values the impedance is kept low across a wide range of frequency and the resonances are kept to a minimum.

But this does not take the parallel resonance into account. If parallel resonance did not matter we could decouple everything with a few tantalum caps.

It sounds like this is a simple design, but have you tested worse case? Try the situation where the address and data bus both change from all

0s to all 1s at the same moment (assuming this processor can do that). The DSP I last designed with would switch both data and address busses at the same time. Put a high speed scope probe (with a very short ground) on a separate output from this part that is set to a 1 and watch the glitch, that is your total bounce including the inductance from the power pins and the plane bounce. Also measure the glitch on a power pin and you will have just the power plane noise. After you consider this noise and the other sources such as crosstalk, can you tell if your design is quiet enough. Testing won't do it unless you explicitly test your worst cases.

If you are driving with fast edges, you are driving high current. Series terminated 3.3 volt CMOS driving a 50 ohm transmission line will drive 33 mA per line. It will be much higher if it is not series terminated. Multiply that by 64 and you get 2 Amps! Did you consider this much current in your decoupling calculations? If you don't supply the current from the power plane the caps can't really keep up with the fast rise time of many drivers (< 1 ns). It will create high noise on the planes and can trigger bounce logic level problems.

If you are using an MCU with fully internal memory then we are talking about a different class of design and you can get by with a dozen or so of single value caps.

Reply to
rickman

Probably, but I also think this topic should probably be revisited from time to time as well. As Austin stated in the intro post, there are few reasons to stack caps (unless the dominant cause is lack of adequate capacitance), which simply shouldn't happen if you have a good idea what worst case current spikes from the chip are. That unfortunately isn't specified, because it's highly variable depending on the design, place/route, and other factors. If something is "fixed" by adding some additional medium/low speed capacitance, then you made some wrong assumption, or have a process problem (like poor via plating as I've seen before).

My experience is that there are some designs, which do not work in some packages, even with best possible practice on the user PCB, simply because of the inductance and resistances in the package. My REALLY BAD experience was XCV2000E's in BG560's. I've had similar problems with other parts that are not nearly as clear, but find comfort that Xilinx is improving packaging so they believe that XC4V and XC5V should not be a problem. When I have time, I may revisit the PCB layouts given your wonderful enlightment, and see if there are improvements to be made.

Maybe I'll even risk getting a few XC4VLX100, XC4VLX200's, or XC5V parts and giving it a try. I suspect there may still be some land mines that are related to very dense designs which are optimized to one combinatorial delay based around SRL's, with minimum inter LUT routing dominating the timing and power requirements, and may result in very short power bursts several times the average current. In the largest parts, the clock skew may hide this, thus preventing the current stackup. If it's possible to juggle the routing to balance the clock skew, there may well still be "perverse" ways of getting the parts to fail, that can also be accidentally invoked by placement and routing variations. It would be interesting to spend a few days to verify this, and see if it really is safe not to worry about unexpected worst case stackups.

In the end, we may have to move to the next level, and get rid of the packages all togather. When I asked Xilinx about getting raw tested die for direct user PCB attach last year they were a very resistant. With half, or better of the inductance still remaining in the package, it's getting tougher, even with best practice, to meet the demands for high performance applications.

thanks .. and Have Fun!! John

Reply to
fpga_toys

Hi David, I think the main issue at stake in this thread isn't the impedances per se, but resonances between the various components of the board assembly. I recommend that you try using spice simulations to see these resonance mechanisms for yourself. This certainly increased my understanding of the subject. The LTSpice files I posted might help get you started.

In summary, I think we have (at least) two different methodologies in this thread.

1) Rick's teacher has presented a way to prevent resonances between bypass caps and power planes. These resonances can be substantial because of the high Q of the plane capacitance. He prevents this serious resonance by using a bunch of different valued capacitors to move and spread out the resonance. This introduces new parallel resonances between these different valued caps, but these aren't as bad as the original plane resonance because the caps have low Q. 2) For FPGA boards, I suggest a solution whereby we dispense with the power plane. Hence no serious resonance, as we have no high Q components. Use one value of decoupling cap to prevent resonances between different values. Pick a value with crappy Q. We have lost the very high frequency decoupling capability of the plane capacitance, but that was no use anyway as we can't couple this plane capacitance to the device we're using because its package has too much inductance (from its balls and vias plus the PCB vias). Instead, we use a bunch (maybe even a bigger bunch than in (1)) of bypass caps (very) near the device and a small 'mini-plane' to parallel them together. The money you've saved by removing a PCB layer pays for the extra caps.

Both methods will work. Each has pros and cons. But I use methodology 2). :-) As package technology advances, I will re-evaluate this position. I may also need to learn how to use a 3-D modelling package, as lumped simulation is not much help beyond 1GHz.

Cheers, Syms. p.s. In both methods, the over-riding key issue is to have a decent ground. Without that, forget everything.

Reply to
Symon

Awesome summary Symon :)

Reply to
fpga_toys

I'll chip in one more point (which I have not data for, but discussion may be enlightening :-)..

Even above the frequency at which the die won't see the noise due to the package inductance, the noise on the planes may still cause problems in passing EMC emissions tests, so you still have to be careful at the top end.

Out of interest - do you consider how your mini-planes resonate at high frequencies?

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
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Reply to
Martin Thompson

I'm now beginning to get a better idea of the parallel resonance problem. In particular, it's the high Q of the plane capacitor that causes the biggest issue.

You're right - I've been looking at the capacitors separately rather than how they affect each other.

The card is not nearly as advanced as many of the cards made by people in this group - it's highest frequencies are in the 150 MHz range, with relatively few fast traces (there is a databus to an sdram chip, but the only lines I really have to be careful with are the clocks to the sdram chips at 75 MHz), and everything is fairly low power.

What you (and Symon) have given me is a number of ideas about the problems on higher speed cards, and possible solutions to the problems, along with a better understanding of what I don't know and need to learn about if I am ever involved in making faster cards. I'm not a specialist in this field (I'm mainly an embedded programmer), and know that cards using the bigger and faster FPGAs would be completely out of my depth, but I appreciate the tips I pick up here for my cards anyway.

I've done some worst-case (or close to worst case) testing of the databus, but it would probably be a good idea to do some better measurements during such tests.

I've done some rough calculations, but the drivers are not that fast - although I appreciate the levels of the current spikes. I have not seen any indications of noise problems or bounce, but perhaps I need to do some more careful measurements.

The memory is not internal on this MCU, but I agree it's a different class to designs using much higher speed devices and signals. I'm not overly concerned about this design, but perhaps future cards will have DDR memory and need more care.

Reply to
David Brown

Symon ha escrito:

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ps,

There is still one thing that I don=B4t fully understand about Rick's method. The resonance of the power plane capacitance with the capacitors inductance depends on the number and package of the capacitors ( the capacitors inductance is related to the package). I don=B4t see how changing the capacitors value (capacitive) can modify the position or peak of that resonce. IMHO 20 0.1uF capacitors will have the same resonance with the power plane as 20 0.001uF capacitors (or even 10 0.01uF plus 10 0.001uF)

So far I've been decoupling using different value capacitors because that's the method that Xilinx recomends, but whithout seeing much logic in the use of small value capacitors (if higher value can be used in the same package). Now I think that Simon=B4s metod makes more sense.

Regards

Reply to
al82

Do you know the edge rate of your drivers on the SDRAM interface? They are likley sub-nanosecond which means you need to consider both the SI issues and the power distribution issues. It was not that long ago that many PC motherboards could not work correctly with a third or fourth SDRAM module plugged in because they did not do their homework on SI issues. Now we are up to DDR2 speeds and are seeing the same problems. But that does not mean you can ignore SDRAM SI issues. The circuits are still the same and the edge rates can get you if you don't give them their proper attention.

If you have a working board you can measure the ground/power bounce rather easily. I think I described it before, but here it is again. Write code to switch all the data bus and address bus signals in the same direction at one time. Set some other output near these pins to a constant level. Watch this constant output and see if you get a glitch on this pin when the others change. This is the amplitude of the bounce on your device. There may be additional noise on the power/ground planes that comes from other chips so this may not be the worst case noise the chip will see.

On a separate note, I can't believe some of the things we do here. Our digital circuits are part of RF equipment so we are typically very concerned with even low levels of noise in the RF region. To make sure our boards are quiet we have an RF person review the design and board layout. I was assisting on a design for a simple MCU board with an attached GPS receiver. The RF guy was very concerned about various noise sources that had burned him in the past and did a lot of what I thought was overkill in the power distribution. I just found out that he had the 6 layer stackup done with two ground planes and no power plane! I suggested to the layout guy that it would be ok to flood fill the signal layers with power plane and he said they are doing that, but connecting to ground instead of power!!! So there is no effective bypassing on this board above a couple hundred MHz and the freq of the receiver is around 1.5 GHz. Do you think we will see any interference?

Reply to
rickman

The data I saw suggested that larger boards have plane resonance issues at lower frequencies. The mini-plane approach would deliver less overall capacitance compared to a full plane but the resonances would be much higher in frequency since the transmission-line effects of the "open" at the board edge have a much shorter quarter-wavelength for a higher frequency before plane resonance.

Reply to
John_H

ass

he

using

ance.

caps,

The problem with trying to analyze this sort of design is that the board does what it wants and does not care what you or I think it should do. If you want to understand what is happening, you can read Ritchey's book or you can do some simulations and measurements yourself. Obviously others are not convinced, but what I learned in this course and read in his book has me convinced about the utility of the method.

I don't want to criticize anyone else's technique since I can't say for sure what will work and what won't. But analyzing a design on paper can give you a false sense of security until you simulate it or test it. Rather than state an opinion, try it!

On the other hand, you should also consider that the SRF of the different value caps is different. So why would they have the same resonance when coupled to a plane?

Reply to
rickman

Yes, if you eliminate the plane altogether you will not have any resonances!!!

A resonance is not totally bad. It is only bad if the impedance is above the level that you can tolerate. The goal is to maintain a low impedance over a wide range of frequencies. If you make the plane smaller you may push the resonance higher in frequency, but you also increase the impedance across the high end of the band.

At edge rates of a nanosecond or less, the power plane capacitance is the only capacitance that is effective to preserve the edge and to reduce the resulting EMI. If you cut your planes into tiny regions that have a fraction of the capacitance of the total board you will be greatly increasing the impedance at these frequencies. There is no other way to reduce this impedance.

The resonance peaks in impedance can easily be minimized by using low Q capacitors. If you avoid C0G type parts and work with a range of capacitance values you should not see a problem. If you use a tiny power plane you will have a high impedance at the higher frequencies and your signal edge rates and EMI will suffer.

The only down side to using multiple capacitor sizes is that you have three line items on the BOM in place of one. On most of my BOMs I already have at least two of these values anyway. I like to keep my BOMs clean, but it seems silly to let this goal drive your decoupling solution.

Reply to
rickman

You'll have no resonances but the inductance from the caps you have will put a high upper limit on your impedance, agreed totally.

What is a problem is that the board when in a geometrical resonance - not an LC issue but a transmission line issue where the open ends of the plane reflect energy back around a quarter wavelgnth - the upper end of the transmission-line resonance is an extremely high impedance. It's these values that very high frequencies can't have plane-level decoupling benefit them. Different areas of the board will experience different resonances and even different resonant modes based on the geometry. These modes can be predicted to help determine "better" places for caps that *can* still help on large geometry boards.

Absolutely. There's less distributed plane capacitance because there's less plane. It's an issue of tradeoffs if your point of interest is a geometry-driven resonance that can't easily be quashed with available caps.

One way would be to use more esoteric ground/power distribution layers. While the early distributed capacitance solutions beyond simple thin dielectrics produced 2 mil FR4 layers between power and ground, there are other materials available now (none of which I've had the joy to use) down to 8 mil, some using higher dielectric constant materials to increase the distributed capacitance further. The geometry can stay the same with better capacitance or the geometry can be reduced without compromising the distributed capacitance. It's a cost vs. perceived benefit issue here.

The low-ESR C0G (NPO) style caps aren't necessarily a no-no, it's just that the SRFs have to be closer (hence more cap values) in order to reduce the LC resonance peaks between SRFs brought on by high-Q caps. It's probably best to stick with low ESR but there may be some solutions where the higher SRFs (I'm assuming they're better, not certain) may provide better coverage in a specific high frequency range.

I would have thought more than 3 line items would be appropriate but the information I saw might not have realized the benefits from low-Q caps.

I really like the possibilities with "good" bypassing design.

Reply to
John_H

The situation might not be so bad. When an RF engineer is interested in quiet power, there are filters between any noisy digital power planes and the power for the RF section, effectively eliminating any bypass gains achieved from the beautifully bypassed (but still RF-sensitivity compromising) power planes.

There is a large variety of RF caps specifically used for in-line power decoupling that are effective *only* at the high frequencies partly because that's the only frequency of interest in the RF device. An oscillator at

1.5 GHz cares little about what's happening at 200 MHz if that 200 MHz noise has been filtered out before hitting the effective 1.5 GHz bypassing.

The truely effective board level decoupling can result in much better mixed-signal performance where discretes are connected directly to the shared power plane. True RF still seems like a much different animal to me where grounds really are king (with properly filtered and cascaded power distribution is regal as well).

Reply to
John_H

your

and

the

Hi Martin, As John says in his post, both the capacitance and dimensions of the 'mini-plane' is much smaller than a big plane, so its capacitance and quarter-wavelength is much smaller. This means that at the frequency at which the bypass caps and plane would potentially resonate is where the capacitors' ESR is huge. According to the Murata tool I linked in a previous post, a 0402 X5R 1uF cap has an ESR of 1 ohm at 3GHz and rises with frequency beyond that. This ESR damps any potential resonance. Another reason why crappy Q is a good thing in this case. Cheers, Syms.

Reply to
Symon

So, the resonance is between the sum of the capacitance of the plane and the bypass cap and the inductance of the bypass cap. (The plane has very little inductance to contribute.) Using different values changes the total capacitance, I guess. The sims do show this effect, but they also show new resonances between different valued caps, but these are generally smaller than the plane resonance as the ESR of the bypass cap damps any resonance. Cheers, Syms.

Reply to
Symon

Rick, To me, it sounds as if your RF guy is doing exactly the right thing. It's what I would do. I'm interested in what coupling paths you see which could produce interference.

Anyway, I'll let you into a little secret! At my workplace a few years back, an RF/Microwave guy started working. He's now moved on, but we remain good friends. I've learnt so much stuff from this guy, indeed, enough to be confident in posting and backing up my ideas and thoughts about bypass caps and PDSs on a public forum.

So, why not buy your RF guy a few beers and listen to his thoughts on why he did what he did? You might even like to print out bits of this thread and ask his opinion. If nothing else, it'll be cheaper than taking a class. ;-)

Anyway, be sure to report back on what happens with the board.

Best regards, Syms.

Reply to
Symon

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