placing addiional caps across existing caps to reduce noise

To the subject at hand: placing additional caps across existing caps does not reduce the noise (unless the dominant cause is lack of adequate capacitance).

The reason why the noise is bad is that the L (as in Ldi/dt) is most likely the largest, and most dominant factor, in the form of the via and traces to the bypass capacitor.

Many times people have placed additional caps on top of the the existing caps and wondered why the noise is not reduced: well, you did not change the L in the equation, did you. So why did you expect V to change?

You may have moved the resonant frequency (more often not), but often people make the mistake of assuming that a 0.1uF requires a 0.01uF and a

0.001uF in parallel. You can see that if the series L is dominant, you haven't even moved the frequency by more than a few percent by the small amount of additional capacitance.

Unfortunately, once the via and trace L is large, there is no way to make the noise less, withpout making a whole new pcb (re-layout).

More that once we have had to inform a customer that there is "no hope" for their pcb because the series L in their layout is dominant, and there is no way to reduce it.

And, we have then helped them re-layout their pcb and making their system work just fine (as, if you know what you are doing, this is not a hard problem to solve).

Mark Alexander's power distribution application note represents the latest state of our power distribution sysem "knowledge."

As we learn more, we will certainly update the applications note.

Again, my apologies to the group for a new thread, on an old subject.

Austin

Reply to
Austin Lesea
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This is certainly true, and been the cause for more than a few re-layouts.

At the same time, the chip carrier PCB in most BGA packages also has via's (probably a lot smaller) which add to the series L which are beyound your control, so you only have half, or less of the series L variable in your control. This is even more difficult with older BG series parts where there are also bonding wires in the equation.

The only reason for stacking a mix of caps in checkout, is just to verify that it's not a bulk capacitance problem.

It would be nice if Xilinx specified both the R and L for these chip carrier PCB's vias/traces, along with chip carrier interplance capacitance, and current profiles to better model both power system performance, and I/O performance. Or at least gave firm numbers on what the user PCB values can be, before the combine result would be unstable by design.

Reply to
fpga_toys

What do you think about the idea that if the caps are connected directly to good low impedance power planes that the location of the caps are not critical at all. I have been discussing this in comp.arch.embedded and have not gotten much negative feedback except some claim that more is always better and that multiple values are not needed.

A recent SI/EMI class I took says that you can put a relatively small number of caps pretty much anywhere on the board as long as they are coupled to the power planes with no traces, just the via. This gives a very low impedance connection to the planes and the planes give a very low impedance connection to the chip. It was also shown that to get a low impedance over a broad bandwidth multiple values are needed to push the impedance down and the parallel resonance up. High loss capacitors (X7R/X5R vs. C0G) were also recommended to reduce the signficance of the parallel resonance.

Does any of this sound correct to you? It was sure convincing in the class and appears to be a very sure way of getting low noise on the power planes and thereby on the chip power pins!

Reply to
rickman

On proto boards I'm always worried about process controls, and frequently avoid flying probe testing since it only tests a small number of the connections anyway. One of the concerns has always been plating managment, so where I can on proto (and most production boards) I still place the caps across the pwr/gnd vias when I can, simply to take the via/plane plating reliability out of the question. Stacking caps on problem boards, is just a second check, as high frequency caps are the only thing at the pads normally, so a little bulk stacked on it just takes the via plating out of the question a bit.

On production boards, the vendors will generall work with you to optimize plating density across the board, so it's much less of a problem.

Reply to
fpga_toys

If you have problems with via plating, don't you have much bigger problems to worry about than cap placement?

Reply to
rickman

On production boards, it's simply not acceptable.

On proto boards, it's only a problem for high current vias (pwr/gnd), which is largely avoided if that's where the caps are too, since it averages out the current spikes and reduces any voltage drop across the bad plate. Even then, the few places that it was a problem at all, where the small BGA vias ... everything else is large enough you never see it.

Reply to
fpga_toys

I suppose you can always break out the micro/milli ohm meter and double check every power ground via to plane .... but it's just easier to add bulk caps as a check for problem boards, since the BGA is already mounted anyway, and no way to reliably ohm it.

Reply to
fpga_toys

...

On that subject: The webpages for Spartan 5 talk about "Virtex-5 sparse chevron packaging effectively positions bypass capacitors on-substrate"

I didn't find any further information about these capacitors.

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes

Uwe Bonnes schrieb:

Spartan-5 ? is Spartan-4 going to be skipped?

Antti

Reply to
Antti

Ouch!

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes

Austin Lesea schrieb:

Larger caps can contribute a significant portion to the L. In that case the second capacitor helps because you reduce part of the L by adding a smaller L in parallel to a portion of the big L. The inductance for an SMT capacitor is in the range of 50pH to 3000pH. This is about the same range as vias of various sizes.

Kolja Sulimma

Reply to
Kolja Sulimma

Rick,

Via in pad (basically no trace) is best. Placement is not critical, as long as you have via in pad, and planes.

But even so, the diameter of the vias, and their lengths can be critical, and still be the dominant factor.

It is all about the lop that is formed (see the HK sparse chevron presentations, as I think he said it best).

Do you need a broad low impedance? I would say that it is most unusual that a pcb has to work over all frequencies. The system is usually designed with a finite number and range of clocks (33 MHz, 266 MHz, 78 MHz, for example). I would counter that rather than a flat broad low impedance, you could do better to target just the frequencies you care about.

High loss/low loss is a red herring: I have never seen a case where the type of capacitor made any difference at all. I would be interested if anyone has made a board where high loss/loss loss caps actually made a measurable difference,

Aust> Aust>> To the subject at hand: placing additional caps across existing caps

Reply to
Austin Lesea

Uwe,

The on-chip capacitors are a compromise. They are intended to improve the energy storage (reduce supply sag, reduce jitter, etc.) but they are not intended to be the entire solution, nor should they affect the overall PDS design. Given that we have room for maybe 16 total capacitors, and their values (each) is ~0.1uF, they are at best useful, and at worst, provide little improvements at all.

Since we can not choose these values for a specific operation frequency, they may be useful for only some frequencies, and not useful at others.

We have worked with customers who wish to completely model everything, and when we supply the geometric model (suitable for Ansoft, or other E&M tool), we also supply the capacitors for that package being modeled.

I would say that for the 0.1% of customers who are pushing the part to its absolute limits in their design, that these capacitors may be important, and they may be required (as input values) in order to properly optimize/design the rest of the PDS.

If you desire more information about a particular package, please contact your FAE, who will be able to contact the factory to get the values, and on what supplies, the internal capacitors are.

Austin

Uwe B>

Reply to
Austin Lesea

Kolja,

I think you are doing extremely well if your cap inductance is dominant.

I have seen many cases where the vias and traces to the capacitors are more than 1 nH.

Many do not realize just how bad a small diameter via going through half a pcb can be.

Aust> Austin Lesea schrieb:

Reply to
Austin Lesea

Ahmen ....

Reply to
fpga_toys

Where exactly is the loop you are referring to? Some would say it is back to the chip through the power pins. It appears to me that it only has to include the power planes. If it is back to the chip, then placement should be critical.

I understand what you are saying, but I think the Ritchey method is very simple and effective. The range of change in the inductance of the various via placements is not so large that it swamps out the inductance of the cap which I would say dominates. In any event, if you just use a range of cap values to provide multiple SRFs you end up with a very broad low impedance power plane. This was shown both in simulation and in measurements.

Ritchey also discussed this, since knowing your frequency range is actually critical to any power decoupling approach. He showed that the IO noise for a series damped transmission line can be calculated assuming a current profile of the rise time limiting the slew (max freq) and the duration controlled by the roundtrip delay (min freq). This trapezoid has a given spectral profile which is not controlled by the clock at all. So even if the entire design is run from the same clock you can expect a lot of power noise to show at a wide range of frequencies.

I can't say a design failed because of low loss caps, but Ritchey had very clear measurements that showed a strong ESR peak where the caps resonated with the plane. By using caps with a higher ESR the resonance was damped out and the impedance "hole" was eliminated.

BTW, one of your people was in the class. He seemed to get a lot from it too. I have misplaced his card or I would ask you to say hi to him for me. He seemed like a good guy! :^)

Reply to
rickman

I got the impression from somewhere, that the bga carriers that are direct die attach also have their own power and ground planes, so that an individual chip pwr/gnd couples to those planes, which are then coupled in parallel to the users PCB power planes. It seems that if this is true, and Xilinx provided both some serious bulk capacitance and mixed high speed, that the current profiles thru the parallel vias to the users pcb should be much calmer, and not have a lot of harmonics. The planes would probably be a hacked up mesh at best, but better than 4mil traces.

Hmmm ... that explains some experimental data, thanks!! And contrary to this thread, why stacked cap debug configurations sometimes seem to actually work since the 0.1uf and 1uf "bulk caps" stacked over the

0.01uf would have a different ESR's and help damp this by flattening the current profile in both the cap's and via's inductive response. The 0.01uf caps high current recharge path would be the two bulk caps instead of resonating with the pwr/gnd plane, and the 0.1uf would more slowly reduce the current source to the via inductor, tapering off rather than more abruptly running out of charge early, thus smoothing/damping the via inductors resonate current response.

Or did I miss something?

Reply to
fpga_toys

I guess in theory the planes on the BGA could resonate with the board power planes and produce a pretty high frequency hole, but that would largely depend on the inductance of the connection and I expect you would need to measure that to see how bad it is.

Mostly it is important to design low impedance, broadband power planes and then I would treat the package as inductance in the path to the chip causing ground/power bounce. Adding caps or planes to the package will not mitigate the bounce problem.

I'm not sure your analysis is accurate, but it is a rare case where adding caps will hurt. The smallest cap will produce the highest frequency parallel resonance. Any lower frequency parallel resonance will be mitigated by the capacitive effect of the smaller cap. It is hard to analyze this stuff by thinking about it. It is much better to simulate it or to measure it. If nothing else you can check out the Ritchey book, "Right The First Time, A Practical Handbook on High Speed PCB and System Design, Volume 1". He is promising a Volume 2, "Included in this text will be a thorough treatment of EMI; a comprehensive description of the PCB fabrication process and PCB materials; a detailed examination of simulation tools and their use and a complete discussion of Gigabit and higher signaling protocols."

Reply to
rickman

My memory is fuzzy on this (and other topics for that matter) but I think via in pad creates an assembly issue because the pad of the part is physically blocking the via (by design). Unfortunately I don't recall the specifics, maybe someone else recalls.

Unless you already understand the issue (that I've conveniently forgotten) I would suggest that whoever is going to be building your boards be consulted to understand if there are appropriate tradeoffs that can be made prior to planning to use 'via in pad' since manufacturability is also generally a concern that at least must be taken into consideration and evalutated.

KJ

Reply to
KJ

Via in pad is a bad thing if you don't have filled vias since they would otherwise wick the solder away from the component. This "solder thief" can present a reliability problem beyond initial build because of trapped gasses even if the connection started out as good.

Filled vias are an extra process that will cost a little money but most PC vendors can do it. The benefits in lower inductance can be great.

Reply to
John_H

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