After compiling few FPGAs, I have found this phenomenon. When the design occupies a small fraction of the FPGA, par throws the stuff loosely spread all over the FPGA...like ugly zigzags... When the design occupies 80% of the FPGA, par kompresses my design densely into the bottom
60% of the FPGA, leaving top 40% loosely occupied...then it tell me it failed route...:( Weird!What may I do besides manual floorplanning?
Kelvin