Hello all,
I realized something interesting today, adding registers in your design can actually reduce the slice usage (in Virtex-II Pro). For example, I started a design with minimal pilelining to keep it simple at first.
Before pipelining, I had the following usage: Slices: 2433 Flip Flops: 2287 LUT: 2981 (seems a bit high, might be a typo in my notebook)
After pipelining, I get: Slices: 1973 Flip Flops: 2615 LUT: 2069
I knew from the begining that pipelining would be needed but I didn't realize that it could save me some slices (on top of the obvious max frequency increase).
I might as well throw in a question while I'm at it. Now I need to pipeline further (need to go from 78 MHz to 100 MHz) but it gets more complicated, I would need to pipeline the function "to_signed (from float32)" from the VHDL-200X float_pkg. Any suggestions on how to do that? I read somewhere that one can add an extra level of registers, and let the tool figure out how to do the register retiming. I would use xst with the "register_balancing yes" flag, but I'm not sure how good xst is at register balancing.
Thanks.
Patrick Dubois