Hi All,
i request somebody who worked on or having knowledge about Physical interface for PCI express(PIPE) to reply for my below query.
i am trying to understand the PIPE interface for my application. INTEL has no where specified the electrical interface of the PIPE if we use the PHY as an external component and PCI express link layer in FPGA. when i spend hours together to find this, finally i got one device from PHILIPS PX1011a which supports SSTL2 standard.
is there any standard electrical interface defined for this kind of application? if it is, can anybody can share the link to those documents to me.
thanks in advance
S.RANGA REDDY