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Phase Offset in Xilinx DDS Core

I'm now using Xilinx DDS Core(v5.0 in ISE7.1i).

I wanna generate 2 channels of sine wave, same frequency, different phase offset.

But in the practice, the frequency of Sine wave turns out right, the phase offset wrong. Even if I give both two channels 0 offset, they two are not in a same phase.

at first I thought that may coused by my pulling down WE signal after I write a data into the DDS core. But I found that's not the key after I tried giving all the data in and then pulling down WE signal.

I can not find the reaseon now. Does anyone could help? Any suggestions would be appreciated.

Reply to
AdamS
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"AdamS" schrieb im Newsbeitrag news: snipped-for-privacy@g14g2000cwa.googlegroups.com...

Is there a reset for the phase accumulator in the core?

Regards Falk

Reply to
Falk Brunner

only one sentence got to the key point

Thanks a lot^_^

Reply to
AdamS

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