Periodically delayed clock

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I'm preparing designs for a CPU that will be coded in Verilog on
a Terasic Cyclone V GX starter kit dev board.

I have a clock running at N MHz, and I have some logic that may
take longer than the allotted time to complete (as N increases
and the time to complete the logic each cycle decreases).

Rather than re-design my logic to use pipeline stages, I would
like to do something like add a BUSY flag that would be raised
when various logic units are busy, and lowered when they're no
longer busy, so the clock is held before the next cycle actually
triggers.

Would something as simple as this work (using an input clock,
busy, busy reset, and an output clock2 that drives the system):

    CLK  = Cyclic N MHz clock
    BUSY = Asserted by various logic units when busy
    BRST = ~CLK
    CLK2 = trigger clock (on ~CLK && ~BUSY && BRST):

         __    __    __    __    __    __    __    __    __
CLK   __|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__
                   ______
BUSY  ____________|      |____________________________________
      __    __    __    __    __    __    __    __    __    __
BRST    |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  

      __    __    __          __    __    __    __    __    __
CLK2    |__|  |__|  |________|  |__|  |__|  |__|  |__|  |__|  
                       held

It would also seem I need to trigger each test to go high only
on @negedge CLK so there are not partial clocks triggered, and
that it would need to track @negedge BRST for going low.

Is there an easier / different way to do this?

Thank you in advance.

--  
Rick C. Hodgin

Re: Periodically delayed clock
tirsdag den 27. november 2018 kl. 17.42.46 UTC+1 skrev Rick C. Hodgin:
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don't gate the clock unless you really really have to, it is a recipe for headaches  

clock everything on the same clock and use a clock enable instead




Re: Periodically delayed clock
On Tuesday, November 27, 2018 at 12:36:13 PM UTC-5, snipped-for-privacy@gmail.c
om wrote:
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 headaches  
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+1

Clock gating adds logic and delay to the clock path.  This makes timing ana
lysis very hard to do and the automatic tools will all but give up.  Certai
nly you won't be able to trust them anymore.  In your simulations the added
 delays can muck up things as well.  

As LL has said, use clock enables and multiple clock cycles.  

  Rick C.  

  Tesla referral code - https://ts.la/richard11209

Re: Periodically delayed clock
On Tuesday, November 27, 2018 at 1:13:25 PM UTC-5, snipped-for-privacy@gmail.com  
wrote:
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.com wrote:
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or headaches  
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nalysis very hard to do and the automatic tools will all but give up.  Cert
ainly you won't be able to trust them anymore.  In your simulations the add
ed delays can muck up things as well.  
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LL, Rick C, thank you for your reply.

I'm not sure what "clock enables" means.  Is there an example?

--  
Rick C. Hodgin

Re: Periodically delayed clock
On Tuesday, November 27, 2018 at 2:12:27 PM UTC-5, Rick C. Hodgin wrote:
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m wrote:
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il.com wrote:
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 for headaches  
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 analysis very hard to do and the automatic tools will all but give up.  Ce
rtainly you won't be able to trust them anymore.  In your simulations the a
dded delays can muck up things as well.  
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FFs can have enables on them so they don't take action until the enable is  
high.  In VHDL code it looks like this...

if (rising_edge(fast_clk)) then  
  if (clock_enable_a = '1') then
    Q_out <= D_in;
  end if;
end if;

You can use separate clock enables for separate sections of your circuit as
 needed.  The clock enables are treated like any other logic circuit in you
r design with timing constraints of 1 clock cycle.  The logic feeding the D
 input to an clock enabled FF only needs to be constrained as the clock ena
ble logic dictates, 2 clock cycles, 3 clock cycles, etc. according to the o
peration of your design.  

  Rick C.  

  Tesla referral code + https://ts.la/richard11209

Re: Periodically delayed clock
On Tuesday, November 27, 2018 at 4:05:54 PM UTC-5, snipped-for-privacy@gmail.com  
wrote:
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s high.  In VHDL code it looks like this...
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as needed.  The clock enables are treated like any other logic circuit in y
our design with timing constraints of 1 clock cycle.  The logic feeding the
 D input to an clock enabled FF only needs to be constrained as the clock e
nable logic dictates, 2 clock cycles, 3 clock cycles, etc. according to the
 operation of your design.  

Part of my goals on this project are to create a static design that can be  
clocked down to 0 MHz and still maintain it state, to clock at 1 Hz and sti
ll work, to clock on a mechanical external trigger, and to run on the vario
us system clocks.

My thinking has been that if I'm able to get it working properly at my targ
et clock speed, then everything else should work if I underclock it, and ev
en bring it down to a halt.

With such a design, would the ability to have variable clock pulse widths s
till be something to be avoided?  Or is the whole idea of such a wildly var
iable clock speed a pipe dream? :-)

--  
Rick C. Hodgin

Re: Periodically delayed clock
On Tuesday, November 27, 2018 at 4:24:16 PM UTC-5, Rick C. Hodgin wrote:
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m wrote:
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:
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 is high.  In VHDL code it looks like this...
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t as needed.  The clock enables are treated like any other logic circuit in
 your design with timing constraints of 1 clock cycle.  The logic feeding t
he D input to an clock enabled FF only needs to be constrained as the clock
 enable logic dictates, 2 clock cycles, 3 clock cycles, etc. according to t
he operation of your design.  
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e clocked down to 0 MHz and still maintain it state, to clock at 1 Hz and s
till work, to clock on a mechanical external trigger, and to run on the var
ious system clocks.
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rget clock speed, then everything else should work if I underclock it, and  
even bring it down to a halt.
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 still be something to be avoided?  Or is the whole idea of such a wildly v
ariable clock speed a pipe dream? :-)

Absolutely avoid variable width clock pulses for the reasons given.  Clock  
enables are the perfect way to slow your speed, enabling the design only on
 the clock cycles you wish to advance the processing.  By removing the enab
le the entire design stops.  Raise the enable for one clock cycle and the d
esign advances one step.  

It is always good to consider how you will debug a design in the chip.  But
 you should be testing in simulation to get rid of 99.99% of the bugs befor
e you ever load it into an FPGA.  

  Rick C.  

  Tesla referral code -- https://ts.la/richard11209

Re: Periodically delayed clock
On 27/11/2018 17:36, snipped-for-privacy@gmail.com wrote:
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I also agree with statement,however for completeness most (if not all)  
modern synthesis tools will remove the AND gate in front of the clock  
input and re-connect the "gate signal" to the FF's CE pin (there are  
other constructs as well).

FPGA are used for ASIC prototyping and for this reason most synthesis  
tools can handle ASIC coding styles like gate clocks, ripple counters,  
clock muxes and they even convert DesignWare blocks.

My additional advice to Rick would be spend some time on adding pipeline  
stages and simply stall the units if no input data is available or feed  
them with NOPs. If you want to give units more clock cycles delays then  
look into multicyle path constructs and constraints (which can sometimes  
be a real pain). You might also want to add some assertions (on the path  
control logic) to confirm the path is always multicyle (>1 clock cycle).

Good luck,
Hans
www.ht-lab.com

Re: Periodically delayed clock
How would I implement a clock enable differently than I'm doing here?


    CLK  = Cyclic N MHz clock  
    BUSY = Asserted by various logic units when busy  
    BRST = ~CLK  
    CLK2 = trigger clock (on ~CLK && ~BUSY && BRST):  

         __    __    __    __    __    __    __    __    __  
CLK   __|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__  
                   ______  
BUSY  ____________|      |____________________________________  
      __    __    __    __    __    __    __    __    __    __  
BRST    |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|    

      __    __    __          __    __    __    __    __    __  
CLK2    |__|  |__|  |________|  |__|  |__|  |__|  |__|  |__|    
                       held  

It's like my BUSY signal would effectively be ~ENABLE, wouldn't it?
CLK still runs consistent and periodic, but the advances are triggered
off CLK2, which could be renamed TRIGGER or something.

??

--  
Rick C. Hodgin

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 10:43:17 AM UTC-5, Rick C. Hodgin wrote:
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I don't see an implementation.  I see a timing diagram where you appear to be gating the clock.  I'm not sure what you are thinking or what you are trying to say.  

I gave you a snippet of code that showed a clock enable.  Did you understand the code?  How about if you write some code that will implement your idea and compare that to the code I gave you?  

  Rick C.  

  Tesla referral code -+ https://ts.la/richard11209

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 11:32:07 AM UTC-5, snipped-for-privacy@gmail.com wrote:
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The CLK2 output is the trigger for the next event.

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The little bit above is close to the code, but there are some caveats on which edge to trigger.

I'll put on my thinking cap and get back to you.

--  
Rick C. Hodgin

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 12:22:12 PM UTC-5, Rick C. Hodgin wrote:
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.com wrote:
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ote:
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 to be gating the clock.  I'm not sure what you are thinking or what you ar
e trying to say.
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You seem to be speaking in your own terms.  I don't know what a "trigger" m
eans.  Digital design signals generally have clocks and logic.  Logic can b
e clock enables or data.  By "trigger" do you mean a clock enable?  If you  
are talking about a clock enable, it should not be generated by gating the  
clock.  

Let me make this simple.  NEVER GATE THE CLOCK when working in FPGAs.  In f
act, I will make this even more general, NEVER USE THE CLOCK AS PART OF THE
 LOGIC.  There may be a very few cases where it makes sense to use the cloc
k as part of your logic, but they are exceedingly few and you have to under
stand all the implications.  I'm not willing to go through all the importan
t issues with someone who is dealing with the basics of logic design.  So f
or now learn the basics, then maybe you can learn the rest later.  

So for now consider all logic to be the same, based on other logic signals  
only and not the clock.  This also applies to your busy reset.  


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stand the code?  How about if you write some code that will implement your  
idea and compare that to the code I gave you?  
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which edge to trigger.
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Don't try to worry about "which clock edge".  Always work with the positive
 edge until you better understand what you are doing.  Like using the clock
 in logic, there are few situations where working on the opposite edge of t
he clock will gain you any advantages and it adds significantly to the issu
es of verifying timing.  

The clock should be used for one thing only, to drive the clock input of FF
s, preferably all triggered from the same edge.  

  Rick C.  

  Tesla referral code +- https://ts.la/richard11209

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 12:44:02 PM UTC-5, snipped-for-privacy@gmail.c
om wrote:
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 means.

The trigger is the signal given to advance the stepper.  Here is an illustr
ated example from a reference CPU design written for the purposes of instru
ction and education:

    Scott CPU -- Begins at 2:33 into the video.
    Click the link directly to advance to that point:

    
https://www.youtube.com/watch?v=NKYgZH7SBjk&t=2m33s


I already have a five-stage pipeline.  As clock speeds go faster, some oper
ations will take longer to compute than the clock allows.  It is only on th
ose stages that I want there to be a delay here.

So my thinking has been:  I'll take the clock, which is steady at whatever  
clock speed it's running, and then not use it as input into that stepper co
mponent, but will introduce delays to consume an extra clock cycle where re
quired due to the delays on certain instructions.

I apologize for using my own terminology.  I have never taken classes on th
is subject.  This is all me figuring out how it should be done in logic, an
d then trying (with much difficulty) to translate it into the needs of real
-world tools.  I also encounter resistance when I approach others with my t
hinking, rather than the hard and fast specs / terms other people are used  
to hearing.  To be honest, it's a little bit frustrating for me because I h
ave been able to figure all of this out on my own, and what I'm getting los
t on is the mechanics of making it happen in real-world tools, and not the  
theory underlying it.

--  
Rick C. Hodgin

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 1:13:21 PM UTC-5, Rick C. Hodgin wrote:
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.com wrote:
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r" means.
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trated example from a reference CPU design written for the purposes of inst
ruction and education:
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erations will take longer to compute than the clock allows.  It is only on  
those stages that I want there to be a delay here.
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r clock speed it's running, and then not use it as input into that stepper  
component, but will introduce delays to consume an extra clock cycle where  
required due to the delays on certain instructions.
Quoted text here. Click to load it
this subject.  This is all me figuring out how it should be done in logic,  
and then trying (with much difficulty) to translate it into the needs of re
al-world tools.  I also encounter resistance when I approach others with my
 thinking, rather than the hard and fast specs / terms other people are use
d to hearing.  To be honest, it's a little bit frustrating for me because I
 have been able to figure all of this out on my own, and what I'm getting l
ost on is the mechanics of making it happen in real-world tools, and not th
e theory underlying it.

Ok, you are trying to generate an output called "trigger".  You might try a
nother name.  So what is your question?  

Thinking in your own terms and names means you will find it hard to communi
cate with others.  I have given you enough information to understand how to
 delay your circuit using a clock enable.  Is there anything you don't unde
rstand regarding what I have given you?  

Personally I think your problem is you are trying to build an aircraft carr
ier before you understand how to build a hinge.  It would be much better if
 you tried working on much simpler projects and worked up to your massive C
PU design.  But you are free to learn any way you want.  

So what is your question?  

  Rick C.  

  Tesla referral code ++ https://ts.la/richard11209

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 1:41:05 PM UTC-5, snipped-for-privacy@gmail.com wrote:
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I agree.  I'll work on it.  Will you help me get there?

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    if (rising_edge(fast_clk)) then  
      if (clock_enable_a = '1') then  
        Q_out <= D_in;  
      end if;  
    end if;

What is D_in here?

--  
Rick C. Hodgin

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 2:14:05 PM UTC-5, Rick C. Hodgin wrote:
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         FF
     +--------+
     |        |
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     |        |
     |  Q_out |---->  
     |        |
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     |        |
     +--------+

Is this more clear?  

  Rick C.  

  Tesla referral code --- https://ts.la/richard11209

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 2:19:21 PM UTC-5, snipped-for-privacy@gmail.com wrote:
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I understood the throughput.  I don't know what "FF" means, and I don't
know where D_in comes from.  What's it wired to?

--  
Rick C. Hodgin

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 2:42:35 PM UTC-5, Rick C. Hodgin wrote:
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FF means Flip Flop, the basic element of storage in digital logic.  D_in comes from your logic.  It is any signal you want it to be.  

I don't know if we are simply having communication problems because you are not familiar with the most fundamental nomenclature of digital logic design or if you don't understand the concepts of digital logic.  I find both ideas equally implausible.  

What do you call a flip flop?  What would you use as the data input?  

  Rick C.  

  Tesla referral code --+ https://ts.la/richard11209

Re: Periodically delayed clock
On Wednesday, November 28, 2018 at 2:49:23 PM UTC-5, snipped-for-privacy@gmail.co
m wrote:
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comes from your logic.  It is any signal you want it to be.
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re not familiar with the most fundamental nomenclature of digital logic des
ign or if you don't understand the concepts of digital logic.  I find both  
ideas equally implausible.

I understand concepts.  I even know flip-flop, but the FF abbreviation wasn
't on my radar.

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I have thought of them as bit storage.  And as I understand their use, they
 are explicitly set to 0 or 1, and do not actually flip flop.  They maintai
n the state specified as of the time of their last setting, so they output  
continually as a bit buffer.

I think D_in would be wired to my BUSY signal, and the SET input would be a
sserted on each clock's rising edge.  This would consistently set the FF to
 0 or 1 based on the BUSY input, and it would sustain throughout the entire
 clock cycle, being re-SET each time to the new state.

--  
Rick C. Hodgin

Re: Periodically delayed clock
onsdag den 28. november 2018 kl. 21.06.57 UTC+1 skrev Rick C. Hodgin:
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com wrote:
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n comes from your logic.  It is any signal you want it to be.
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 are not familiar with the most fundamental nomenclature of digital logic d
esign or if you don't understand the concepts of digital logic.  I find bot
h ideas equally implausible.
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sn't on my radar.
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ey are explicitly set to 0 or 1, and do not actually flip flop.  They maint
ain the state specified as of the time of their last setting, so they outpu
t continually as a bit buffer.
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 asserted on each clock's rising edge.  This would consistently set the FF  
to 0 or 1 based on the BUSY input, and it would sustain throughout the enti
re clock cycle, being re-SET each time to the new state.
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rewind ....

the code was:

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that is a flopflip with clok enable; at every rising edge of fast_clk  
D_in get "stored" and appears on Q_out, IF and only if clock_enable is high

you busy signal goes to clock_enable
  


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