pcix core in XC2VP7

Hello, I'm developing a pcix-card and I will use the PCIX-core from Xilinx in a XC2VP7-5FF896 FPGA. Does anyone know if there is the need for using special pins of the FPGA to connecet the PCIX-signals to the bus-connector. Or can I use any FPGA-pin for any PCIX-signal? Thank you for answers! Matthias Müller

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Matthias Müller
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The databook I have (older) mentioned some banking restrictions but it looks like they have disappeared with newer software.

Make sure you obey the PCI-X trace length restrictions on the card. I would establish the orientation of your FPGA on the card and then choose a pinout that lines up with the edge card pins. Worked for me.

Mark

Matthias Müller wrote:

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Mark Schellhorn

Hi,

You should use the PCIX IOs listed in Datasheet.

These IOs meet the PCIX specification standards.

Regards, Muthu

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Muthu

Thank you! Looks like any user I/O can be used with the pci-x standard. Have you considered the XAPP653 for over- and undershoot handling? Xilinx recommends to regulate Vcco to 3.0V for all banks with pci-x standard in order to keep values within the maximum FPGA specification.

Matthias

Mark Schellhorn schrieb:

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-- Matthias Müller Fraunhofer Institut Integrierte Schaltungen IIS

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Matthias Müller

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