PCIe question

The lane signals should be AC coupled: a. on the motherboard between the controller and PCIe socket b. on the PCIe card between the FPGA GTP and PCIe PCB connector c. on both

? thx, Vasile

Reply to
vsurducan
Loading thread data ...

The spec says all _transmitters_ shall be AC coupled. You just lead the RX line directly to your component.

In terms of your a) b) c) options, the answer is therefore c) but only the TX line(s).

By the way as far as I remember, there is some Intel doc recommending placing the cap at 1/3 of the distance from plug to component (i.e. closer to the plug than to the component).

Reply to
Charles, NG

Also if you're designing a PCIe plug-in card, remember that the signal names on the connector are based on the motherboard. So you need to connect your transmitter to the receive signals (PERP0/PERN0 ...) and your receiver to the transmit signals (PETP0/PETN0 ...). Since the Rx and Tx signals are on the opposite board surface, it is very hard to correct swapped signals using wires! I got bit by this on my first PCIe design.

Reply to
Gabor

Thx for attentioning but my intention is to route differential signals on stripline (between ground planes) and I guess will be no wire. I'm designing both the PCIe card and the motherboard and...

Vasile

Reply to
vasile

This is new for me. What do you mean with 30KHz beacon at 3.1Gbps ? The 0.1uF impedance is large enough for a Ghz signal.

Reply to
vasile

It is very important to make sure your coupling capacitor is large enough to handle the 30kHz beacons, so *if* (as I do on occasion) you ac couple at _each end of the link_, make sure you used double the recommended value of capacitor if it's a short (in the transmission line sense) link.

Cheers

PeteS

Reply to
PeteS

.075uF (75nF) is the minimum spec. There is also a maximum of 0.2uF (200nF) so theoretically 0.1uF -25/+100 % is good. Z5U or Y5U bypass quality caps won't give you this tolerance. X7R or X5R will. The 1.1 specification talks about 0603 components, but I would think 0402 would work better.

Reply to
Gabor

PCIe (as with most high speed links) uses beacon signals to determine if the 'other end' of the link is active. That beacon is a relatively low frequency pulse to minimise EMC/EMI. 0.1uF is easily sufficient, but at

2.5Gb/s (1.25GHz fundamental) a 100pF cap would be sufficient - the cap recommended in the PCIe spec (you do have a copy right?) is sufficient for the beaconing. (I don't have a copy in front of me, but I seem to remember it's 0.075uF).

Cheers

PeteS

Reply to
PeteS

A major issue is parasitics. 0402 is ok, 0603 is marginal.

As to type, I wouldn't use anything less than X5R anyway for a signal path.

Cheers

PeteS

Reply to
PeteS

The Beacon is one way a wakeup from L2 LTSSM state (deep power save). Depends on whether your Phy implementation supports this method or uses the Wake# or even whether the deep power save feature is supported.

John Adair Enterpo> >

Reply to
John Adair

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.