PCI test bench

There are few different options. If you have time just write our own pci transactor models. It's not such a big task if you have the standard. PCI standard is quite well written, but be aware that the state machines in the end may not be the best way to implement the transactor. Add few more states and everything is easier. My transactor (slave+master) is about 1000 lines of Vera code, and took few weeks to write and verify.

Of course you can buy ready made test solutions. For example Synopsys Designware Verification IP for PCI.

There are also othe vendors that do such models, just use google.

--Kim

Hi Anthony,

This is probably what you are not looking for, but our company's Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core does come with a PCI testbench that is probably much better than Xilinx LogiCORE PCI Ping reference design's simple PCI testbench. We had to develop this pretty extensive PCI testbench (Ping reference design's testbench was a joke for our purposes.) in order for us to stress BDS XPCI PCI IP core against Xilinx LogiCORE PCI. BDS PCI Testbench that comes with the BDS XPCI PCI IP core consists of,

• PCI Arbiter model

• Host to PCI bridge emulator

• 32-bit and 64-bit target PCI device simulation models

BDS PCI Testbench's PCI Arbiter model can handle up to 8 PCI initiator (master) devices. The only limitation it currently has is that it cannot perform hidden arbitration. (Hidden arbitration is GNT# being awarded to another device during a transaction.) Host to PCI bridge emulator is something similar to microprocessor (CPU) inside a computer. Here the designer writes series of HDL code to access the PCI bus, just like what programmers will do when writing a program to directly access the PCI device. Host to PCI bridge emulator comes with the following Verilog tasks and VHDL procedures.

Configuration_Read Configuration_Write Single_Read_32 Single_Write_32 Burst_Read_32 Burst_Write_32

These tasks and procedures can be called, for example, with an address parity error and a certain bit flipped and/or certain number of wait states inserted. Burst_Read_32 and Burst_Write_32 are probably the most useful in this Host to PCI bridge emulator that allows the designer initiate a long (up to 1024 transactions) PCI transaction with user specified wait states, parity error condition, and which bit to flip in case of a parity error condition for each data transferred. If the designer couples Burst_Read_32 and Burst_Write_32 with a random number generator ($random in Verilog), it should be able to perform a random wait state insertion test against a target device. 32-bit and 64-bit target PCI device simulation models are target only PCI devices that can be programmed to act in certain ways. For example, it can be programmed to perform five retries, accept only 3 data transfers, and then terminate the transaction with Disconnect without Data. (Or Disconnect with Data.) It can also be programmed to generate parity error every several transfers during a read transfer with the bit being flipped specified.

32-bit and 64-bit target PCI device simulation models are very effective when debugging an initiator device because initiators need to be able to handle retry and wait state being inserted randomly, and still function perfectly. The current shortcomings of BDS PCI Testbench are the following.

• Currently cannot handle hidden arbitration

• Currently no one can guide the arbiter to behave in a certain way

• Cannot handle interrupt in the way real computers handle interrupt

• It doesn't come with a PCI protocol checker

• It doesn't come with a PCI bus monitor

• 64-bit version of Host to PCI bridge isn't ready yet

Currently, only the Verilog version of the BDS PCI Testbench is ready, and is in the process of being ported to VHDL. Since you mentioned that you already have Xilinx LogiCORE PCI32, you obviously don't want the BDS XPCI PCI IP core. Instead, we can sell (license) you the BDS PCI Testbench only without the BDS XPCI PCI IP core. We now have a introductory special going on for BDS XPCI32 PCI IP core where the BDS XPCI32 PCI IP core commercial perpetual license version normally costs $3,000 for domestic customers/$3,600 for foreign customers. But because of the introductory special, we offer it for $2,000 domestic/$2,400 foreign. Since you want the BDS PCI Testbench only, we can offer the BDS PCI Testbench for $1,000 domestic/$1,200 foreign as part of the introductory special. In addition to that, we still offer BDS XPCI32 PCI IP core and BDS XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) for non-commercial, non-profit, personal use for $100 and $200, respectively. For more information, visit Brace Design Solutions website at

Kevin Brace

Anth> As a licensed user of the Xilinx PCI32 core, where does one get a more

comprehensive PCI testbench (stimulus generator) than what comes with the Xilinx PING example.

--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available 
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com

Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.

We modified the Opencores PCI testbench to provide an engine that would allow us to generate arbitrary PCI cycles.

Regards, Mark

comprehensive

example.

QuickLogic have a nice set of PCI models for both master and target, but I would imagine that they prefer you use them to design-in one of their chips.

-a