The URL would be too long. It's patent 6,601,126, and is available at
There was an EE Times (and other CMP websites) article about this story.
This sounds fishy to me. I've personally worked on SoC designs using only uni-directional busses with various asynchronous peripherals - well before the time this patent was filed. I'd like to see PalmChip try to enforce this patent. The EET article also mentions that FPGAs have been using this kind of technology for a while.
Here are some of the "claims" of the patent:
"1. An on-chip interconnection system, comprising:
a single semiconductor integrated circuit (IC);
a plurality of uni-directional buses disposed in the IC;
a peripheral-bus (p-bus) included in the plurality of uni-directional buses and that uses a simple non-pipelined protocol and supports both synchronous and asynchronous slave peripherals;
a p-bus controller connected to the p-bus and constituting an only bus-master, and including a centralized address decoder for generating a dedicated peripheral select signal, and providing for a connection to synchronous and asynchronous slave peripherals, and further providing for an input/output (I/O) backplane that allows a processor to configure and control any of its slave peripherals; and
an m-bus included in the plurality of uni-directional buses, and for providing a direct memory access (DMA) connection from any said slave peripherals to a main memory and permits peripherals to transfer data directly without processor intervention.
- The on-chip interconnection system of claim 1, wherein, there are included no tri-stated-buses, and no bi-directional buses.
- The on-chip interconnection system of claim 1, wherein, each signal has only a single buffer driver.
- The on-chip interconnection system of claim 1, wherein, any broadcast signals are re-driven by simple buffers with no extra control logic."