Partial shift register extraction in ISE

Hi all,

I'm building a design where I want ISE (8.1) to extract the shift registers in some parts, i.e. where I have inferred SRL counters etc, and not to extract them in other parts. For instance where I have coded multiple stages of pipelining in order to obtain timing closure. Has anybody done this? Partial shift register extraction, that is.

The design is occupying about 50% of a Virtex-2 2000 and running mostly at 200 MHz. This is why I need to insert some pipelining between different stages in the signal path. My intention is to add a few stages to enable ISE to divide the routing in shorter bits.

Any input is highly appreciated

/Johan

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Johan Bernspång, xjohbex@xfoix.se
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Johan Bernspång
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Gabor

Gabor, thanks! Of course a reset statement would prevent ISE from turning the registers into SRLs. I also found out, by browsing through some old course notes from X that duplicated registers named reg_1, reg_2 etc are mapped into the same slice. They should be named reg_a, reg_b and so forth. Maybe that will help as well.

/Johan

Gabor wrote:

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Johan Bernspång, xjohbex@xfoix.se
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Johan Bernspång

Also look in the Mapping Options for "disable register ordering" if this is a problem. In the old days, slice packing was done by the mapper. Now I'm not sure how much difference this makes if you allow the XST synthesis to pack logic into slices. There may be a similar setting for XST, but I couldn't find it.

Regards, Gabor

es

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Gabor

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Johan Bernspång, xjohbex@xfoix.se
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Johan Bernspång

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