Hi all,
I'm building a design where I want ISE (8.1) to extract the shift registers in some parts, i.e. where I have inferred SRL counters etc, and not to extract them in other parts. For instance where I have coded multiple stages of pipelining in order to obtain timing closure. Has anybody done this? Partial shift register extraction, that is.
The design is occupying about 50% of a Virtex-2 2000 and running mostly at 200 MHz. This is why I need to insert some pipelining between different stages in the signal path. My intention is to add a few stages to enable ISE to divide the routing in shorter bits.
Any input is highly appreciated
/Johan