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Partial Reconfiguration clock enable problem

Hello!

I have finished a Xilinx partial reconfiguration design which runs succesfully on my Virtex II Pro. Yet, there is one line of a reconfigurable module which crosses the module boundary. It is the constant clock enable signal for a reconfiguration module which not me but the tool added. This constant is generated in a LUT within the boundaries of another module, yet only connected to a LUT within the correct module (no further connections). I would be happy to know how to remove this boundary corssing signal. Did anybody encounter similar problems or may help me with some hints?

Thanks a lot,

Florian

Reply to
Florian
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HI i am facing problem of 16 clock in my design although planahead says only 8 clocks can be used

Reply to
hiluckydr

If you have 16 clocks then you likely don't understand how to design digital systems. Since you didn't post any actual question or request for anything specific, all I can offer is 'Good Luck'.

KJ

Reply to
KJ

Why do you need 16 unrelated clocks in your design?

Some more information is required. It is unusual to need 16.

There are techniques of creating enables from low speed clock edges that can be used to "eliminate" a clock from a design.

--
Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk
Reply to
Mike Perkins

Does seem pretty unusual.

I can image a data multiplexer that takes 15 signals, each with their own clock, and combines them into one output signal.

There is special clock trees in most FPGAs to distribute low skew clocks to large numbers of FFs. There might be some that need more clocks, but don't need the low skew, and can use ordinary routing for the rest.

-- glen

Reply to
glen herrmannsfeldt

If that is all it is doing, you likely don't need separate high speed clock routing for each, rather as the inputs come on chip they can be immediately synchronized to one system clock.

The skew is always a problem in FPGAs unless you can hand route the clocks. I am told the software will take care of dealing with the skew, the problem is when you have some amount of logic this gets to be a difficult task to manage if the clock routing is not used. I avoid that at all costs.

--

Rick
Reply to
rickman

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