Partial Reconfiguration : 2 reconfig modules

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I'm trying to make a project with 2 reconfig modules. I am using LUT's inside
each module to create constant values (I need those to feed the BUS MACRO), but
instead of using the signal I created to feed the bm's, the tool (PAR?) creates
several "Global_Logic1"'s, and worse, some come from beyond the module frontier!
Of course, when reconfiguration takes place, it stops working. <p>Anyone ever
had a problem like this? Is there a way to stop it from creating all those
signals and just use the ones I tell it to use? <p>Help!!! Thanks.   =)

Re: Partial Reconfiguration : 2 reconfig modules
Update on the problem: somewhere the LUTs are removed from the project. Any VCC
sites I instantiate are removed too. <p>The LUT's and VCC's can be found inside
the .edf, but not later (.pcf). Someone? A hint?

Re: Partial Reconfiguration : 2 reconfig modules

Hello Daniel,

it sounds like you forgot to lock the LUT with the LOCK_PINS constraint in the
ucf file.
Without that NgdBuild or the Mapper replaces your LUT with its 'own' global
logic.

Christian




Re: Partial Reconfiguration : 2 reconfig modules
Hello Christian, <p>Thanks a lot for your help, as you suspected my problem was
the missing constraint. <p>Do you know of any constraints for the VCC primitive?
I used the "LOC" constraint, but it issues me this warning: <p>"WARNING:MapLib -
Property LOC on VCC_clk_dll not supported for simple gates - ignoring."

Re: Partial Reconfiguration : 2 reconfig modules
Hello Daniel,

I'm sorry, I dont know how to constraint VCC sites, either. If you do partial
reconfiguration Xilinx Answer Record 17622 maybe interesting for you.
Xilinx discourages from using VCC sites to drive constants.

Regards
Christian



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