Parameterized Multiplier in Xilinx FPGA

Kiran wrote: : Hi All,

: My design has many multipliers of different input/output widths. I : need to implement it on Xilinx Virtex II XC2V6000 FPGA. I tried using : CoreGen to generate the multipliers but looks like for each set of : input/output widths I need to generate a separate multiplier. This is : very difficult to manage. Is there any way to parameterize the : CoreGen multiplier so that by using one generic wrapper, the same code : can be reused for all the multipliers needed in the design? I am : using Verilog HDL.

: Sorry if this question has already been asked. I tried searching but : could not get any answers.

Using Ise 5.1 and verilog,

wire [18:0] a,b; wire [35:0] c;

assign c = a*b;

invoked a multipler. On Spartan 2 it was built from LUTs, and Spartan 3 the Multiplier blocks were used.

Why then use coregen?

Bye

• You may not want (or need) an 18-bit multiplier

• The design may have exceeded the built-in mults and therefore need other resources.

• You may want a pipelined multplier

• Placement of a core may be more optimal for a particular design need than the built-in mults

You may be able to get away with fewer varieties if you instantiate the largest of a particular class of mults, then rely on the map tools to prune out unused logic. I know it's not a very elegant solution, but neither is the core generator (for the reason you indicate).

Jake

Jake Janovetz wrote: : + You may not want (or need) an 18-bit multiplier

Then define the wires with smaller width

: + The design may have exceeded the built-in mults and therefore need : other resources. I didn't test, but maybe synthesis with fall back to LUT multipliers when all block multipliers are allocated

: + You may want a pipelined multplier

there's an Applikation Note how to code to get pipelined LUT multipliers ( for Block multipliers this doesn't apply)

: + Placement of a core may be more optimal for a particular design need : than the built-in mults

don't fullquote.

Bye

if your synthesis tool (e.g. amplify) supports, u can precisely control the pipelining levels and style of the multiplier inferred by * operator.

regards

--yka