In altera's tool, if a .tdf file uses the parameter for that component, and if you instantiate the component in the schematic, you can change the parameter by right clicking on the symbol. I wonder if there is similar feature with VHDL file in Xilinx ISE's ECS tool. That is a convenient feature because you can instantiate as many time as you want, and just change the parameter in the schematic to customize each one of them.
Thanks, Charles