Historically I have used a VHDL file to embody the constants in a design where possible using meaningful names which can be easily changed.
library IEEE; use IEEE.STD_LOGIC_1164.all; package constants is constant rck_freq : integer := 30; end constants;
I require two sets of constants according to debug or otherwise, I might try:
package constants is if debug = 1 then constant rck_freq : integer := 10; else constant rck_freq : integer := 30; end if; end constants;
But ISE coughs. Can someone enlighten me on the correct way of doing this, if possible?