Hi, I seem to be getting a higher P&R speed (I put a constraint on the only clk I have in the design) than that I got from synthesis. Sometimes by up to
10 MHz. Is that possible? I am using ISE 6.3 and targeting a Virtex 2 1000 -4.Thank you Adrian
Hi, I seem to be getting a higher P&R speed (I put a constraint on the only clk I have in the design) than that I got from synthesis. Sometimes by up to
10 MHz. Is that possible? I am using ISE 6.3 and targeting a Virtex 2 1000 -4.Thank you Adrian
I have seen that too on occasion, usually the very next change to the code fixes it right away:-)
JJ
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