Hello @ VHDL people out there,
I have the following problem. Maybe someone of you has experienced the same:
The signal "input_data" comes from a 12MHz clock domain. Now I want to sample that signal that way that I generate one sample-enable which is close to the center position of the bits. One possibility to do so is to use a over-sampling clock, let us assume
48MHz.When stepping to the signal processing of my design I see that the sampled signal which is in the 48MHz clock domain now has to be synchronized into a 90MHz clock domain.
So my idea was to sample the "input_data" with a sample-enable directly in the 90MHz clock domain.
The problem: 90 is not a multiple of 12. Is there a possibility to sample the 12MHz signal right in the center ?
When using 48MHz sample clock I use a simple counter with which I can define the position of the sampling point.
Any suggestions are appriciated.
Rgds Andre