Over-Sampling

Hello @ VHDL people out there,

I have the following problem. Maybe someone of you has experienced the same:

The signal "input_data" comes from a 12MHz clock domain. Now I want to sample that signal that way that I generate one sample-enable which is close to the center position of the bits. One possibility to do so is to use a over-sampling clock, let us assume

48MHz.

When stepping to the signal processing of my design I see that the sampled signal which is in the 48MHz clock domain now has to be synchronized into a 90MHz clock domain.

So my idea was to sample the "input_data" with a sample-enable directly in the 90MHz clock domain.

The problem: 90 is not a multiple of 12. Is there a possibility to sample the 12MHz signal right in the center ?

When using 48MHz sample clock I use a simple counter with which I can define the position of the sampling point.

Any suggestions are appriciated.

Rgds Andre

Reply to
ALuPin
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Hi,

90/12 = 7.5 and fractional division may be performed by dividing by 7 one cycle and 8 the next. If the jitter is acceptable, the resulting divisor is 7.5.

/Peter

Reply to
Peter Hermansson

"ALuPin" schrieb im Newsbeitrag news: snipped-for-privacy@posting.google.com...

same:

sample-enable

USB??

Sure, just take some smart FSM to track the 12 MHz data signal clocking. Or easier, us a asynchronous FIFO.

Regards Falk

Reply to
Falk Brunner

Sample with a 180MHz clock.

Kolja Sulimma

Reply to
Kolja Sulimma

No matter what approach you use, the only way to sample "exaclty" in the middle of the data bit is to have an analog PLL for clock recovery. If you use an unrelated 48 MHz clock, you can be off by +/- 1/8 bit period if you use an ideal digitally phase locked loop for "effective" clock recovery. A faster sampling rate would provide better than the cumulative 1/4 period.

same:

sample-enable

Reply to
John_H

Or, you may be able to use both edges of the clock to produce a de-facto 180 MHz. Use with care.

Jason

Reply to
jtw

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