I want to build an easy decode-logic in VHDL. My problem is that the value I write to the output isn't stored till it should change :-( Here my simplified code:
testprocess : PROCESS (IN1,IN2) BEGIN IF (IN1 = '1') AND (IN2 = '0') THEN OUT0
Manfred Balik wrote on 11/07/05 16:00:
Maybe you can force Quartus to generate a latch by adding an "ELSE"-condition, like
... ELSE OUT0
How would a default value differ from a latch?
-a
Latch = keep last value, default value = always set to 0 (or 1) if none of the conditions is met (which seems to be what is happening to the OP).
Maybe Quartus aims to avoid latches at all costs and adds logic to make the output go to 0 if none the conditions is met. So if you're really absolutely sure you need a latch, then you have to either instantiate it as a primitive or describe it in a way that leaves no doubt it's supposed to be a latch.
But, as I said, only speculation... never worked with Quartus, and I know zilch about Altera-FPGAs in general, so I'm guessing here.
cu, Sean
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