Ok, hi all, I'm new to fpgas and am having some fun with an Altera UP3 kit.
In the app I'm developing I have a component that I use 8 times in parallel and the problem is that in the logic of this component are two divide by 5 performed on integer variables. I can't use bit shifting obviously, but is there cheap in terms of LEs way to do a divide by 5 other than with a divide? This is killing me because the divides use something like 1500 LEs which is almost 2X larger than the rest of the logic.
If there's no other reasonable way I think I can rearchitect it and make it a divide by 4 and thus make available the use of bit shifting.
Any help appreciated, thanks.
Here's a dump of all the crap quartus seems to be adding for the divide:
Info: Found 1 design units, including 1 entities, in source file ../../../../../../../altera/quartus50sp1/libraries/megafunctions/lpm_divide.tdf Info: Found entity 1: lpm_divide Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_smf.tdf Info: Found entity 1: lpm_divide_smf Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_uig.tdf Info: Found entity 1: sign_div_unsign_uig Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_1od.tdf Info: Found entity 1: alt_u_div_1od Info: Found 1 design units, including 1 entities, in source file db/add_sub_ke8.tdf Info: Found entity 1: add_sub_ke8 Info: Found 1 design units, including 1 entities, in source file db/add_sub_le8.tdf Info: Found entity 1: add_sub_le8 Info: Found 1 design units, including 1 entities, in source file db/add_sub_me8.tdf Info: Found entity 1: add_sub_me8 Info: Found 1 design units, including 1 entities, in source file db/add_sub_ne8.tdf Info: Found entity 1: add_sub_ne8 Info: Found 1 design units, including 1 entities, in source file db/add_sub_la8.tdf Info: Found entity 1: add_sub_la8