hello friends,
For better security, I am porting a design from Xilinx (Spartan3) to Actel (ProAsic3E). The Actel part is very nice and works great. The only problem i have had is that the design becomes bigger and slower than expected. Now, I do understand that some parts of this design translate to bigger logic on the Actel part. I also understand that the xilinx part was bigger and faster [1], and there are some fundamental differences between xilinx CLBs and actel VersaTiles.
What is really confusing however; is that some changes that i was sure will make the design smaller or faster had the opposite effect. and vice versa: some things i considered to be bottlenecks seems to work very nicely on Actel. To put it simple: i don't anymore know what i am doing and it is driving me crazy.
obviously, i need to read more on the subject (and i have read a lot of actel docs already). so please enlighten me with all your actel-specific optimizations tricks, general optimizations guidelines and any other information that may be useful.
in fact, any material about coding style and area optimization is most welcome.
so hit me please with all your wisdom :)
-Burns
[1] i had to say that so Xilinx people don't accuse me of being an undercover Altera engineer :)