optimization tips (badly) needed

hello friends,

For better security, I am porting a design from Xilinx (Spartan3) to Actel (ProAsic3E). The Actel part is very nice and works great. The only problem i have had is that the design becomes bigger and slower than expected. Now, I do understand that some parts of this design translate to bigger logic on the Actel part. I also understand that the xilinx part was bigger and faster [1], and there are some fundamental differences between xilinx CLBs and actel VersaTiles.

What is really confusing however; is that some changes that i was sure will make the design smaller or faster had the opposite effect. and vice versa: some things i considered to be bottlenecks seems to work very nicely on Actel. To put it simple: i don't anymore know what i am doing and it is driving me crazy.

obviously, i need to read more on the subject (and i have read a lot of actel docs already). so please enlighten me with all your actel-specific optimizations tricks, general optimizations guidelines and any other information that may be useful.

in fact, any material about coding style and area optimization is most welcome.

so hit me please with all your wisdom :)

-Burns

[1] i had to say that so Xilinx people don't accuse me of being an undercover Altera engineer :)
Reply to
burn.sir
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.."only the paranoid will survive" (Andy Grove) :-) Peter Alfke, watching you from home

Reply to
Peter Alfke

Well the part might be great, but it is tools & the part that give you the best solution. If Spartan 3 can't satisfy your security needs, you might consider Stratix II, which also has some nice features to solve both the optimization (ALM they call it) and the security issue (non-volatile 128-bit AES key)

*and yes I am an Altera engineer*
Reply to
Karl

"Karl" schrieb im Newsbeitrag news: snipped-for-privacy@g14g2000cwa.googlegroups.com...

and a good one you are - I did never realize that Altera did build in real non volatile key storage into S-II !!

this means that S-II is not really RAM only technology and includes eeprom/flash technology on the same die as well, this is pretty nice as using external battery as it is required for key storage for Xilinx FPGAs is kind a pain

--
Antti Lukats
http://www.xilant.com
Reply to
Antti Lukats

...but the battery solution has the potential to be more secure than having a non-volatile key that can be found by dismantling the device. How much pain would there be if someone stole your design? Cheers, Syms.

Reply to
Symon

"Symon" schrieb im Newsbeitrag news:43ba4f5e$0$15794$ snipped-for-privacy@news.sunsite.dk...

generically, yes

but if Altera did it correctly (key storage on-die not separate die inside the bga package, some other things to be done RIGHT) then its almost as safe as battery. correctly implemented nonvolatile storage for keys would be secure for almost all applications.

--
Antti Lukats
http://www.xilant.com
Reply to
Antti Lukats

The key storage is on-die, so it matches what you want Antti.

Vaughn Betz Altera v b e t z (at) altera.com

Reply to
Vaughn Betz

Just a comment:

And the latest quote we have is for less than $10,000 you can have the key value.

Non-volatile fuses are nice, but be aware that they represent not much real security. Rather, they are a deterrent, as you have to destroy a device to obtain the key.

However, once destroyed, the eprom is still intact, and not you have the bitstream (for all the good that will do you).

Austin

Reply to
Austin Lesea

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