Hi there, i`m trying to get a SoC runinng, which is based on a OR1200 soft-processor in an Spartan 3 device. At the moment the system is working (25 MHz, with UART, external SRAM and an SMSC 9118 connected-done with ISE 7.1.04 and 8.1.02). If i`m trying to re-synthesize the whole system with little changes or removed peripherals, the processor seems to get very instable and the execution of the formerly proper working code fails. I`ve also tried to enable the caches for instructions and data, but the result is the same. I guess, the whole system and the processor is very sensitive for timing problems caused by disadvantageous place and route.
My questions: Does anyone have experience with implementing OR1200 on spartan 3 ? Is there any reference-desing available, which works with the new debug-interface (i doesnt get it to work) and /or enabled caches ? Any hints for getting better implementation-results (settings of ISE, maybe manually place and route)?
any hint would be helpful
.. thanks
Th. Oehme