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OpenCore USB 2.0

Yo! Does anyone know about about a port of an OpenCore USB 2.0 core to either Xilinx, Altera or plain vhdl (of reasonale price).

Reply to
Mounard le Fougueuxt
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am looking for an usb2.0 ip core for plb and opb bus to connect to PPC or Microblaze?

Reply to
Andi

Mounard le Fougueuxt a écrit:

Verilog can be mixed with VHDL, and of course be synthesized alone. Keep in mind that this core, when implemented in an FPGA, must associated with an external PHY chip.

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Reply to
Nicolas Matringe

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