Opencore ddr_controller

Hi, I am trying to do the post_par simulation of the opercore ddr controller(from opencore.org) There is feedback clk in this design which is said to be routed externally to the ddr_clk. Since i cannot do this in the board i am trying to route it througth the fpga for the maximum delay possible. My problem is whenever i try to route the clock i am getting the error message

"Pack 1569: the dual data rate register i_ddr_sdr/fddrd/u1 failed to join a OLOGIC component as required"

i didnt understand the meaning of this error. I tried to generate extra clk(similar to ddr_clk using the fddrrse) but the getting the same error. regards subin

Reply to
subint
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well - the idea is to compensate the IOB delay for the clock with your DCM. This gives you an internal clock that is phase aligned to your external clock ...

just delaying by "the maximum possible" will lead you nowhere ...

you could try to use one DCM to phase shift your internal clock by an adjustable amount and route this clock to you RAM ... you would then have to manually set the delay to phase align internal/external clock

bye, Michael

Reply to
Michael Schöberl

That statement right there says that you need to stop and re-read how to use the core and DDR. The whole point of the feedback clock in any DDR design is to compensate for PCB delays. Trying to emulate these delays in some manner is exactly the wrong approach.

KJ

Reply to
KJ

Reply to
subint

The external feedback is completely unnecessary. If you use a DDR flipflop in the output pad, you can create an external clock which has a very predictable delay in respect to the internal clock. If you use a 90 degrees shifted clock to capture the data into the input DDR flipflop, you'll see there is more than enough timing margin (even more margin than using DQS in combination with IOB delay to capture the data). If trace lengths between the memory are almost equal, using a phase shifted clock is the best option.

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Reply to
Nico Coesel

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