Hello all, I would like to know which open or free HLS (High Level Synthesi s) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesi zable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).
Learning a new language is cumbersome, hence I would like to fill my head w ith only a select few that have promising future.
I have read this comparison
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17/25882/1/Cristal.pdf), which made my think that Chisel might be the way t o go.
sis) tools are gaining widespread use, or are more likely to survive, becau se at the time there seems to be too many, and the advantages of each of th em are not quite clear. The HLS we are talking about should generate synthe sizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera) .
with only a select few that have promising future.
to go.
Hi Leonardo,
I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- whil e it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking. While I've only looked at it briefly myself, LegUp seems to be a worthy ope n/free HLS alternative that is actively maintained
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nto.ca/). I don't think they support Xilinx for the time being, but the abs tractions made by the framework should make it straightforward to port to X ilinx FPGAs (i.e defining the primitives and their relative cost).
I don't think RTL is the correct term here but the point is you feel it requires a lower-lower level abstraction than you would like. Chisel is a bread of the functional language based HDLs. You start with a basic building block (function, or register in HDL) and scale-up quickly - at least that is the idea (?).
I will never understand how any C based language will be considered HLS! Saw a funny tweet the other day:
Computer Science: "In low-level languages like C" Computer Engineering: "In high-level languages like C"
hesis) tools are gaining widespread use, or are more likely to survive, bec ause at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synt hesizable Verilog or VHDL for multiple architectures (at least Xilinx/Alter a).
ad with only a select few that have promising future.
ay to go.
r by either directly using the generated Verilog, or wrapping it as IP core s for importing into Vivado. However, I wouldn't really call it "HLS" -- wh ile it gives higher productivity compared to Verilog or VHDL, Chisel code i s still very close to RTL and requires RTL-like thinking.
pen/free HLS alternative that is actively maintained
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ronto.ca/). I don't think they support Xilinx for the time being, but the a bstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).
Yes, I have already looked at Chisel, and I do agree with you. It seems to have good performance, but it still is very RTL-like, and is not as capable (or supported) as VHDL or Verilog at RTL-level (for example having specifi c architecture instances like RAMs, ROMs or even more important I/O primiti ves is difficult). It just seems like the effort to learn this language com pared to the abstraction/easiness at algorithm level is not very high.
LegUp on the other hand, would provide more abstraction, but it has sub-par results (according to the paper I posted it beats the software implementat ion in performance in most cases, but is always bested by far by other lang uages).
El martes, 9 de junio de 2015, 13:39:23 (UTC-3), Christopher Felton escribi
thesis) tools are gaining widespread use, or are more likely to survive, be cause at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate syn thesizable Verilog or VHDL for multiple architectures (at least Xilinx/Alte ra).
ead with only a select few that have promising future.
way to go.
far by either directly using the generated Verilog, or wrapping it as IP co res for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.
open/free HLS alternative that is actively maintained
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toronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).
Well, the wikipedia page defines it so
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evel_synthesis), not saying this is the ultimate authority in the matter, b ut you at least have to counter this assertion with something better than a tweet.
I guess C is low-level in computer science because you can actually trace m ost of the code one-to-one or one-to-many from C to assembler. In hardware description this is far more difficult to do, some statements are not liter ally translated into HDL code, but rather interpreted, and many assumptions are made. They are different fields. Keep in mind C will not be the highes t HDL language ever, but the first of them (or one of the first).
Why? I wasn't trying to correct anything just stating how I am dumbfounded at the term! Do you disagree with low-high statement? I think it is rather fitting :)
If this is the unfortunate state of terminology, what do we call synthesis of non C languages? Ultra-high, up-in-smoke, etc. etc.
I think this is a better description: "algorithm to gates"
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(there is a book with a similar title)
The HLS term should be language agnostic, it is silly to tie it to C based languages!
Probably because the name was coined in the early 90s (or earlier). In my opinion C synthesis is pointless.
I think these guys kinda got it right (but they based their language on C constructs also - confusing):
El martes, 9 de junio de 2015, 15:08:40 (UTC-3), Christopher Felton escribi
:
ynthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate s ynthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Al tera).
head with only a select few that have promising future.
e way to go.
o far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -
- while it gives higher productivity compared to Verilog or VHDL, Chisel co de is still very close to RTL and requires RTL-like thinking.
hy open/free HLS alternative that is actively maintained
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.utoronto.ca/). I don't think they support Xilinx for the time being, but t he abstractions made by the framework should make it straightforward to por t to Xilinx FPGAs (i.e defining the primitives and their relative cost).
gh-level_synthesis), not saying this is the ultimate authority in the matte r, but you at least have to counter this assertion with something better th an a tweet.
The tweet is true and points at a funny fact. But that doesn't mean that C is not a high level language when talking about synthesis.
The HLS term IS agnostic, the wikipedia article is only focusing about C wh ich is also rather biased (but probably because it is a well known language , and at the time of creation C was considered high level), but mentions: " High-level synthesis (HLS), sometimes referred to as C synthesis, electroni c system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthe sis...". It even includes your "algorithmic" preference for the term as "al gorithmic synthesis".
ce most of the code one-to-one or one-to-many from C to assembler. In hardw are description this is far more difficult to do, some statements are not l iterally translated into HDL code, but rather interpreted, and many assumpt ions are made. They are different fields. Keep in mind C will not be the hi ghest HDL language ever, but the first of them (or one of the first).
in-high-level-synthesis/
The fact that there are less google searches is a fact that can't be ignore d, but it does not mean it is the end. Someone will get it right eventually , and the thing will become very popular, probably at the same time that FP GAs become very popular (mainstream I mean, like arduino with microcontroll ers). If a certain person (or company) is going to make a genius invention (or lead it) in the next two years, then he is thinking about this inventio n starting from now, or even before (and he is certainly at that point very familiar with the problem that he will be tackling). I cannot point any so urce, but I think it makes at least more than 50% of the cases (the rest ju st happened to stumble into greatness by chance).
El martes, 9 de junio de 2015, 17:00:23 (UTC-3), Leonardo Capossio escribi
te:
Synthesis) tools are gaining widespread use, or are more likely to survive , because at the time there seems to be too many, and the advantages of eac h of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/ Altera).
my head with only a select few that have promising future.
the way to go.
so far by either directly using the generated Verilog, or wrapping it as I P cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.
rthy open/free HLS alternative that is actively maintained
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cg.utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to p ort to Xilinx FPGAs (i.e defining the primitives and their relative cost).
High-level_synthesis), not saying this is the ultimate authority in the mat ter, but you at least have to counter this assertion with something better than a tweet.
C is not a high level language when talking about synthesis.
which is also rather biased (but probably because it is a well known langua ge, and at the time of creation C was considered high level), but mentions: "High-level synthesis (HLS), sometimes referred to as C synthesis, electro nic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synt hesis...". It even includes your "algorithmic" preference for the term as " algorithmic synthesis".
race most of the code one-to-one or one-to-many from C to assembler. In har dware description this is far more difficult to do, some statements are not literally translated into HDL code, but rather interpreted, and many assum ptions are made. They are different fields. Keep in mind C will not be the highest HDL language ever, but the first of them (or one of the first).
red, but it does not mean it is the end. Someone will get it right eventual ly, and the thing will become very popular, probably at the same time that FPGAs become very popular (mainstream I mean, like arduino with microcontro llers). If a certain person (or company) is going to make a genius inventio n (or lead it) in the next two years, then he is thinking about this invent ion starting from now, or even before (and he is certainly at that point ve ry familiar with the problem that he will be tackling). I cannot point any source, but I think it makes at least more than 50% of the cases (the rest just happened to stumble into greatness by chance).
For the record the interest in high-level synthesis is slowly decreasing bu t saw an increase starting from 2012. But MORE interesting is the fact that FPGA alone as a search term is decreasing since 2004, and I don't think FP GA are going obsolete any time soon. Turns out that this "EDA" developer ar ticle was really biased
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t=q&tz=). It is clear that HLS is not a mainstream search term, but it is not over (and by HLS, I am talking about any language that infers VHDL/V erilog or gate-level-description)
el Synthesis) tools are gaining widespread use, or are more likely to survi ve, because at the time there seems to be too many, and the advantages of e ach of them are not quite clear. The HLS we are talking about should genera te synthesizable Verilog or VHDL for multiple architectures (at least Xilin x/Altera).
l my head with only a select few that have promising future.
e the way to go.
ts so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HL S" -- while it gives higher productivity compared to Verilog or VHDL, Chise l code is still very close to RTL and requires RTL-like thinking.
worthy open/free HLS alternative that is actively maintained (http://legup. eecg.utoronto.ca/). I don't think they support Xilinx for the time being, b ut the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost) .
i/High-level_synthesis), not saying this is the ultimate authority in the m atter, but you at least have to counter this assertion with something bette r than a tweet.
t C is not a high level language when talking about synthesis.
C which is also rather biased (but probably because it is a well known lang uage, and at the time of creation C was considered high level), but mention s: "High-level synthesis (HLS), sometimes referred to as C synthesis, elect ronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral sy nthesis...". It even includes your "algorithmic" preference for the term as "algorithmic synthesis".
trace most of the code one-to-one or one-to-many from C to assembler. In h ardware description this is far more difficult to do, some statements are n ot literally translated into HDL code, but rather interpreted, and many ass umptions are made. They are different fields. Keep in mind C will not be th e highest HDL language ever, but the first of them (or one of the first).
nored, but it does not mean it is the end. Someone will get it right eventu ally, and the thing will become very popular, probably at the same time tha t FPGAs become very popular (mainstream I mean, like arduino with microcont rollers). If a certain person (or company) is going to make a genius invent ion (or lead it) in the next two years, then he is thinking about this inve ntion starting from now, or even before (and he is certainly at that point very familiar with the problem that he will be tackling). I cannot point an y source, but I think it makes at least more than 50% of the cases (the res t just happened to stumble into greatness by chance).
but saw an increase starting from 2012. But MORE interesting is the fact th at FPGA alone as a search term is decreasing since 2004, and I don't think FPGA are going obsolete any time soon. Turns out that this "EDA" developer article was really biased
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mpt=q&tz=). It is clear that HLS is not a mainstream search term, but i t is not over (and by HLS, I am talking about any language that infers VHDL /Verilog or gate-level-description)
I think the tweet mentioned summarizes this discussion pretty well; there i s no rigid definition of the "high-level" in high-level synthesis :). For me it's not very high level as long as it is converting between equival ent abstractions (e.g. Chisel internally creates a directed acyclic graph o f registers, muxes and operators directly from the description, which can b e viewed as RTL).
Regardless, be it C-to-gates (Vivado HLS/SDSoC) or OpenCL for FPGAs, it see ms to me that the trend is picking up for "FPGAs for software programmers" (see also
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Probably with good reason seeing how several major players seem to be interested in making FPGAs "the next big thing in acceleration" -- Intel acquiring Altera and rumors of Xeons wi th integrated FPGAs, IBM OpenPOWER systems with FPGA accelerators over CAPI , Micron acquiring high-performance FPGA card makers Convey and Pico Comput ing, and so on. As long as the ecosystem thrives and the tools improve, I'm happy :)
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