OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)

Hello,

I'm trying since yesterday to interconnect the opencore mac to a microblaze design. After several problems solved, I'm stuck.

The "Generate netlist now works fine" but When I try to "Generate bitstream", I have three errors from NgdBuild :

ERROR:NgdBuild:604 - logical block 'wb2opb_0/wb2opb_0' with type 'wb2opb' could not be resolved. A Pin name mispelling can cause this, a missing edif or ngc file, or the mispelling of a type name. Symbol 'wb2opb' is not supported in target 'spartan 3'. ERROR:NgdBuild:604 - logical block 'opb2wb_0/opb2wb_0' with type 'opb2wb' could not be resolved. A Pin name mispelling can cause this, a missing edif or ngc file, or the mispelling of a type name. Symbol 'opb2wb' is not supported in target 'spartan 3'. ERROR:NgdBuild:604 - logical block 'wb_ethermac_0/wb_ethermac_0/maccore' with type 'eth_top' could not be resolved. A Pin name mispelling can cause this, a missing edif or ngc file, or the mispelling of a type name. Symbol 'eth_top' is not supported in target 'spartan 3'.

For the wb_ethermac core, I've created a file that includes the eth_top of the ethernet mac core on opencore and present the interface to the outside world. I've done this as a ISE project then I synthetized it to have a .ngc file (because I have both VHDL & Verilog there) then I created an IP from this netfile and my vhdl top file.

Any one has a clue on what to do ? Has anyone make this work ? (I'm using ISE/EDK 6.3)

Thanks,

Sylvain

Reply to
Sylvain Munaut
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I want to do exactly what you do. but i'm stuck to the netlist problem.

I use the wb2opb from ascic.ws and now i want to use some opencore ip to plug to my microblaze. so if you can send to this ng what you have done to make it work i'll apreciated

regards

Jonathan "Sylvain Munaut" a écrit dans le message de news: 420fb7ae$0$22479$ snipped-for-privacy@news.skynet.be...

Reply to
Jonathan Dumaresq

Hi Sylvain,

To make your custom IP accessible in XPS, you'll need to create PSF conformed directory structure and interface files (PAO/MPD/BBD). The Create/Import Peripheral Wizard from EDK can help you on this.

Since you already have the netlist (.ngc) and a wrapper HDL, you shouldn't have problem to use the wizard's import flow to import your mac core. After importing, you can use your custom IPs like any other EDK cores bundled in the tool.

Let me know if you have any questions regarding the wizard.

thanks, y> Hello,

Reply to
Yong Zhu

could you give me what you have done to make it pass the netlist problem ?

here the result i have:

Managing hardware (BBD-specified) netlist files ...

opb2wb (opb2wb_0) - C:\EDK\project\test1\system.mhs:37 - Copying (BBD-specified)

netlist files.

ERROR:MDT - opb2wb (opb2wb_0) - C:\EDK\project\test1\system.mhs:37 - BBD

parameter is undefined in the MPD

ERROR:MDT - platgen failed with errors!

make: *** [implementation/opb2wb_0_wrapper.ngc] Error 2

Done.

regards

Jonathan

"Sylvain Munaut" a écrit dans le message de news: 420fb7ae$0$22479$ snipped-for-privacy@news.skynet.be...

Reply to
Jonathan Dumaresq

Glad to know I'm not alone ;)

Well, finally I got a bitstream ! But ... it doesn't work as excpected so I'm not sure that what I've done is good.

So finally I decided to try a smaller problem, just take Microblaze + UART + opb2wb + opencore_simple_gpio and try to make this work.

Here's what I'm trying right now (writing this msg as I'm doing/testing it ;) From ground up :

  • First step : Install the opb2wb --------------------------------

- Extract the opb2wb_v1_00_a from the tar.gz and put it into your personnal pcore dir - Edit the bbd file and suppress the first column (C_FAMILY) to just leave the first line So you should have

Files ###########...##### opb2wb_v1_00_a.edn

- Edit the mpd file and rename the 'opb_rst' into 'rst' (only the lowercase one. leave the OPB_rst untouched ). - Edit the netlist file (.edn) and change the creator program to "none" So you have (program "none") instead of (program "xilinx stuff ...") The ngcbuild don't like to work with edif netlist created by ngc2edit and tells you to use the original ngc instead but we don't have it ...

*** At this point, adding a opb2wb to an existing/working design and making all wb connections external works (I mean you can produce a bitstream. I don't know if the wrapper works or not ... ****

  • Second step : Creating a wb_gpio_simple EDK-compatible core -------------------------------------------------------------

- I've used the simple_gpio core as a base to create my own very simple gpio_core ... And I'm still at this step and won't finish tonight ;) I already send this which may help you.

Note that some steps might be unecessary, I just wrote that as a collection of all the things I made to make it generate a bitstream.

Sylvain

Reply to
Sylvain Munaut

thank you ...

I will try that

this is what i tought just try a simple gpio with the wrapper

regards

jonathan "Sylvain Munaut" a écrit dans le message de news: 42111c81$0$321$ snipped-for-privacy@news.skynet.be...

Reply to
Jonathan Dumaresq

could you sebd me a copy of the file you have ?

snipped-for-privacy@cimeq.qc.ca_nospam

just remove _nospam to send me this e-mail

regards Jonathan "Sylvain Munaut" a écrit dans le message de news: 42111c81$0$321$ snipped-for-privacy@news.skynet.be...

Reply to
Jonathan Dumaresq

Hi Yong

The main problem we have is not really with XDK. We'd like to use some cores that don't use a opb bus but a wishbone bus. Someone made some wrapper available in the form of EDK core but they seems incompatible with the current EDK. Look at my other post for the details of what correction were necessary.

However I have a problem importing a core. Since I don't know verilog I wrote a VHDL file that includes some verilog code and I would like to make this a EDK core. I couldn't find how to do mixed rtl with the wizard so I created a ISE design with my mixed vhdl/verilog design and synthetized it with my main vhdl as top level. I took the ngc file and used the top level vhdl when the wizard asked for the hdl top. But that didn't work exactly like I excpected ... First I'm not sure on how to make the wizard understand 'inout' (bidirectional) ports, there seems to have issue with mysig_T mysig_O mysig_I of which I'm not sure. Second during the bitstream generation I have this error :

ERROR:NgdBuild:604 - logical block 'wb_ethermac_0/wb_ethermac_0/maccore' with type 'eth_top' could not be resolved. A Pin name mispelling can cause this, a missing edif or ngc file, or the mispelling of a type name. Symbol 'eth_top' is not supported in target 'spartan 3'.

with wb_ether_mac.vhd being my vdhl top file and maccore an instance of eth_top which is defined as verilog. Now, if I also synthetize eth_top as toplevel and copy the resulting ngc file in the implementation directory and relaunch the xflow.bat the XDK left there, it works ...

Maybe I'll just learn the verilog basics to do my wrapper in verilog ;)

Sylvain

Reply to
Sylvain Munaut

"Sylvain Munaut" a écrit dans le message de news: 420fb7ae$0$22479$ snipped-for-privacy@news.skynet.be...

I have the same probleme. I have copied you source code and try to make bitstream and i get the same error.

do you have corrected ?

I thing his happen because you remoce the C_FAMILY in the bbd file. but i really not shure about this.

regards

Jonathan

Reply to
Jonathan Dumaresq

Yes, I didn't notice that error because I didn't make a clean between my tried of yesterday and today's.

After the generate bitstream failed, copy the .edn file of the opb2wb wrapper into the implementation directory of your edk project and rename it to opb2wb.edn

I didn't yet found why this is needed ... it should be done automatically ! (or an equivalent)

Don't think so. Not removing it leads to other problems earlier. And in EDK-wizard generated core the C_FAMILY is not there.

Sylvain

Reply to
Sylvain Munaut

Yes, I have seen this thread, and also had a few private emails from people having problems.

The real problem is that there are no clear guidelines as to how to create truly portable netlist distributions. I have searched the answer database, and the xilinx web site in general, but all information I was able to find was incomplete at best.

Could somebody from Xilinx (or anybody else who has been successful doing this) post a step by step tutorial as to how to create portable netlist distributions ?

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

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Your Partner for IP Cores, Design, Verification and Synthesis

Reply to
Rudolf Usselmann

"Rudolf Usselmann" schrieb im Newsbeitrag news:cusrop$tmj$ snipped-for-privacy@nobel.pacific.net.sg...

Hi Rudi,

I think a bus bridgeing component for EDK can not be implemented fully as netlist at all, not with current state of the tools, and maybe never.

So at least one file of the ip core should be HDL source the remaining can be netlist. The parameters are handled in the HDL part of of the core.

Antti

Reply to
Antti Lukats

To solve the Ngbuild problem at bitstream generation

Another step : Rename the .edn file to just opb2wb (without version). Also don't forget to ajust the name in the bbd file as well.

Then it generate a bitstream just right.

Sylvain Munaut

Reply to
Sylvain Munaut

Hi Rudi,

I was one of the private e-mail you receive.

I would like to know what you have done to make it work in your environement ?

How did you test it ?

whith what wishbone core ?

etc..

Jonathan "Rudolf Usselmann" a écrit dans le message de news: cusrop$tmj$ snipped-for-privacy@nobel.pacific.net.sg...

Reply to
Jonathan Dumaresq

I also create a edk core from the wizard and take a look in the mpd file. I see in the mpd file under ## Generics for vhdl or Pa...

PARAMETER C_FAMILY = virtex2p, DT = STRING

This is probably what they need to the ncg build error ... And again i'm not shure

regards Jonathan

Reply to
Jonathan Dumaresq

Nope

look at the additionnal step I posted today a few hour ago. It now builds fine.

But it doesn't seem to work ... Has someone ever managed to use it ?

Sylvain

Reply to
Sylvain Munaut

yes i con buit it too..

When I look at the system.pbd, I expected to to see a new bus for the wb. But i did'nt see it. I don't know if we need to see it or not.

But i see that the wrapper is connected to the opb bus as a slave.

The other question that i have is how to built a edk-core compatible with verilog file ?

As i can see ther is only the vhdl file that can be use to make an edk core compitible.

so if anyone have any idea of what we have to do to plug a simple wishbone GPIO connected to opbbus via the wrapper....

Jonathan

"Sylvain Munaut" a écrit dans le message de news: 42124499$0$2614$ snipped-for-privacy@news.skynet.be...

Reply to
Jonathan Dumaresq

"Jonathan Dumaresq" schrieb im Newsbeitrag news:N_sQd.23200$ snipped-for-privacy@charlie.risq.qc.ca...

no it would not show. pretty much any not directly supported bus would now show in PBD diagram

both verilog and vhdl can be used, VHDL support in EDK is a bit better but verilog is useable too

Antti

Reply to
Antti Lukats

No you won't see a new bus. This wrapper just export all wishbone bus signals as port. Then you need to connect them manually.

Yes, the opb2wb wrapper translate OPB access to WishBone access. So it's an OPB Slave and a WishBone master.

Just use the wizard and you can use a verilog design. But AFAIK, you can't easily use a mixed verilog/vhdl ...

Sylvain

Reply to
Sylvain Munaut

hi,

I have beeen able to generate the netlist with the gpio of opencore.

But as you said, the wrapper doesn't connect them together directly. I don't know if there is a easy way to plug it together intead of playing with the generated file from xst ?

I have some problem with the include verilog file. for now i have put the content of the included file in the top file to get the netlist to work .. Is there a simpliest way to make included verilog file pass to the netlist generator ?

regards

Jonathan

Reply to
Jonathan Dumaresq

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