Hello,
I have a microblaze system containing an OPB_SPI core. It used to work without adding special timing constraints for this core It seems that I have a timing problem now that my FPGA is getting full The data coming from the SPI core is now shifted by one bit. I hav noticed that the SPI_OPB uses a seperate clock, constraining this cloc used to help but I think that I should add more constraints.
Has anybody had a similar problem? The xilinx site gives no info on th required timing constraints for this core.
thanks and best regards, Karel D