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April 20, 2006, 10:53 am
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I have a microblaze system containing an OPB_SPI core.
It used to work without adding special timing constraints for this core
It seems that I have a timing problem now that my FPGA is getting full
The data coming from the SPI core is now shifted by one bit. I hav
noticed that the SPI_OPB uses a seperate clock, constraining this cloc
used to help but I think that I should add more constraints.
Has anybody had a similar problem? The xilinx site gives no info on th
required timing constraints for this core.
thanks and best regards,
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