Hi,
I am designing an OPB Peripheral which has to act as a master and a slave on the OPB Bus . I am not happy with the IPIF master logic functionality provided by Xilinx . I am trying to design the master logic support myself , but the VHDL code for the Xilinx implementation is not provided in any of the directories .. Does any one have any documents / app notes , which discusses guidelines for the master logic design?
thank you venu