opb_ethernet timing constraints

Hi,

I'm using EDK 6.3i under linux (release 12.3) and I'm trying to instantiate an ethernet controller on my virtex 4 board (avnet xc4vlx25). I'm always getting errors from the PAR tool saying that timing constraints are not met, even if I try harder to synthetize.

I've tried a lot of different options in synthetizing and place and route tools, but nothing changes, and now I just don't have any idea of what I could try. As I'm using the builtin ethernet controller, I'm not supposed to modify anything in the design of it I suppose, so what could I try? Is it possible to build a valid system by ignoring timing constraints?

I include the report of the PAR tool in the message:

Starting initial Timing Analysis. REAL time: 12 secs ERROR:Par:228 - PAR: At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical timing constraint summary follows. This summary will show a MINIMUM net delay for the paths. Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify the problem paths. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE, consult the Xilinx Development System Reference Guide "TRACE" chapter.

Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.

-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels

-------------------------------------------------------------------------------- NET "ETH_RXC_BUFGP" MAXSKEW = 2 nS | 2.000ns | 0.000ns | N/A

--------------------------------------------------------------------------------

  • NET "ETH_RXC_BUFGP" PERIOD = 40 nS HIG | 40.000ns | 5.480ns |
2 H 14 nS | | |

-------------------------------------------------------------------------------- NET "ETH_TXC_BUFGP" MAXSKEW = 2 nS | 2.000ns | 0.000ns | N/A

--------------------------------------------------------------------------------

  • NET "ETH_TXC_BUFGP" PERIOD = 40 nS HIG | 40.000ns | 2.033ns |
1 H 14 nS | | |

-------------------------------------------------------------------------------- TSTXOUT_ethernet = MAXDELAY FROM TIMEGRP | 10.000ns | 3.261ns |

1 "TXCLK_GRP_ethernet" TO TIMEGRP "PADS" 10 | | |

nS | | |

--------------------------------------------------------------------------------

  • TSRXIN_ethernet = MAXDELAY FROM TIMEGRP " | 6.000ns | 6.350ns |
2 PADS" TO TIMEGRP "RXCLK_GRP_ethernet" 6 n | | |

S | | |

-------------------------------------------------------------------------------- TSCLK2CLK90_ddr_controller = MAXDELAY FRO | 2.875ns | 1.376ns |

0 M TIMEGRP "OPB_Clk_ddr_controller" TO TIM | | |

EGRP "Clk90_in_ddr_controller" 2.875 nS | | |

--------------------------------------------------------------------------------

3 constraints not met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.

Bertrand Rousseau

Reply to
Bertrand Rousseau
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I was going to suggest using Base System Builder (BSB) to build an example project and then use the relevant parts about the Ethernet controller.

However, when I look at the BSB file from their website, the Ethernet controller is commented out.

formatting link

It's probably worth asking Avnet why that is since the whole point of BSB is to provide a starting point for user designs to help avoid this sort of issue...

Paul

Bertrand Rousseau wrote:

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Reply to
Paul Hartke

Hi

I have also built a system with opb_ethernet core. For me als

constraints were not met like yours but my system works fine. I thin they can be ignored. If u want, u can implement that separately in IS and optimize the same

Sabar

Reply to
sabari

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