One issue about free hardware

Step 4c. It needs to be programmed in a language that your small target audience have heard of! How many Verilog/VHDL coders also know OCaml? C or Java and you might have a chance...

Cheers, JonB

Reply to
Jon Beniston
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BRams are a very special case since most of the time the 2 address are different so the 2 clock domains are fully independant. If the address should be the same then the result of the 2 concurrent writes is undefined but the user should have taken care about that. given that, the synthesis should be able to handle it with a warning for same addresses.

regards

johnjakson_usa_com

Reply to
john jakson

Sure, but it seemed like the OP was suggesting that synthesis tools should support everything possible in the language.

Cheers, JonB

Reply to
Jon Beniston

That's certainly a point when you are looking for code contributions, and for many open source projects it makes sense to consider that when choosing the language. But for something like Confluence, I don't think that Tom is looking for so much in the way of direct coding help at the moment - feedback and ideas are important, along with contributions to the library, examples and documentation (how many good Verilog/VHDL coders are also good at "normal" software development, especially something as specialised as implementing functional programming languages, regardless of the language?). I am a great supporter of choosing the right language (or right tool of any kind, for that matter) for the job - popularity might be one consideration, but it's not the only one. In fact, why would anyone be interested in confluence in the first place if they were not happy to consider new languages? The choice of ocaml makes a lot of sense here, actually - it is a functional programming language itself (with bits of imperitive language added - sort of the opposite of Python, but for the same reasons), so it matches the style of confluence programming well. It was actually top of my "languages to learn when I have the time" list, but confluence sneaked in on top...

Reply to
David Brown

Another interesting question about the proposed code above is, during a given simulation cycle if both clocks rise at the same time, which executes first in simulation?

Can you re-write the code so that one always has wins or if both happen a the same time an 'X' is generated on d?

Cheers, Jim

Reply to
Jim Lewis

Same as in the real world, the result is indeterminate.

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Rick "rickman" Collins

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rickman

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