Once synthesized RAMs are vanishing in WebPACK 8.1i03

Hello all,

Using WebPACK version 8.1i03 initially synthesized RAM vanishes later in the design??? The design works perfectly OK in WebPACK version 7.1i04, so I would assume that something drastic as this should not happen. The VHDL code also works on Altera FPGAs. I am using Spartan3 here.

I must be doing something obviously wrong, but what? Anyone can shed a light on it? It would be much appreciated.

, The design is the 8051-microcontroller, version 1.4, with patches from

Initially all RAM's are synthesized as in the 7.1i version, but are later largely removed. The VHDL code of one of the RAMs can be found below. The directory with the complete design can be found at

But here are the relevant (i think) parts of the log:

FROM THE SYNTHESIS REPORT: =========================

Synthesizing Unit . Related source file is "/net/users/sietse/FPGA/versie-8.1i/8051/geheugen.vhdl". WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. Found 8192x8-bit single-port block RAM for signal . ----------------------------------------------------------------------- | mode | read-first | | | aspect ratio | 8192-word x 8-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | data in | connected to signal | | | data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- Summary: inferred 1 RAM(s). Unit synthesized.

AND SIMILAR FOR THE OTHER RAMs. AND THEN LATER: ==============================================

Macro Statistics # Block RAMs : 3 128x8-bit single-port block RAM : 1 16384x8-bit single-port block RAM : 1 8192x8-bit single-port block RAM : 1

SO THE RAMs are synthesized initially! ====================================== THEN A NUMBER (7) OF STRANGE INFOs: ===================================

INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed

DON'T KNOW WHAT THIS MEANS. AND THE FINAL (synthesizer) REPORT NOTES: =========================== # RAMS : 2 # RAMB16_S1 : 1 # RAMB16_S9 : 1

SO MOST RAMs ARE GONE!!! ======================= =======================

What is going wrong here? Anyone an idea?

I also installed the WebPack on two different machines.

Regards, Sietse Achterop Computing Science department University of Groningen

PS. I want to use this design in a number of courses that I am giving here.

=============================================================== The VHDL RAM descriptions are like:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;

entity mc8051_ramx is

port (clk : in std_logic; -- clock signal reset : in std_logic; -- reset signal ram_data_i : in std_logic_vector(7 downto 0); -- data input ram_data_o : out std_logic_vector(7 downto 0); -- data output ram_adr_i : in std_logic_vector(15 downto 0); -- adresses ram_wr_i : in std_logic); -- read=0, write=1

end mc8051_ramx;

architecture behav of mc8051_ramx is

type ram_type is array (8191 downto 0) of std_logic_vector(7 downto 0);

signal extram: ram_type; signal int_ram_adr : std_logic_vector(12 downto 0);

begin int_ram_adr