Hello all,
This is a repeat from article 104429 from june 17th to this group, see
Then the problem was in version 8.1i03, and it seemed that it would work with
8.2, but alas it still does NOT work with 8.2i03.Here again the problem in short:
The design is the 8051-microcontroller, now version 1.5, with patches from
The design works perfectly OK in WebPACK version 7.1i04, so I would assume that something drastic as this should not happen. The VHDL code also works on Altera FPGAs. I am using Spartan3 here, and I'm using the linux version on Debian on Pentium IV.
From version 8 on, if MORE THAN HALF of the BRAMs are synthesized, during the end of the synthesis fase it seems as though the blockrams are "thrown away".
The directory with the complete design can be found at
In the synthesis report, mc8051_top.syr, under Low Level Synthesis the following lines appear:
INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed
If the inferred rams do not take half of the available blokrams then these lines DO NOT appear and the generated design just works. A few dozen 8051 programs are running perfectly, using data2mem and a bmm-file to fill the memory.
If the lines appear, the blockrams are largely REMOVED and the bitfile does not work at all.
ONLY changing the size of the RAM can make the problem come and go.
But here are the relevant (i think) parts of the log (file: mc8051_top.syr):
=========================================================================
- Advanced HDL Synthesis * =========================================================================
Loading device for application Rf_Device from file '3s400.nph' in environment /opt/WebPack-8.2. INFO:Xst:1647 - Data output of ROM is tied to register . INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
========================================================================= Advanced HDL Synthesis Report
Macro Statistics # RAMs : 3 128x8-bit single-port block RAM : 1 16384x8-bit single-port block RAM : 1 8192x8-bit single-port block RAM : 1 ......
SO THE RAMs are synthesized initially! ====================================== THEN A NUMBER (5) OF STRANGE INFOs: ===================================
INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed
DON'T KNOW WHAT THIS MEANS. AND THE FINAL (synthesizer) REPORT NOTES: # RAMS : 4 # RAMB16_S1 : 3 # RAMB16_S9 : 1
SO MOST RAMs ARE GONE!!! ======================= =======================
What is going wrong here? Anyone an idea?
I also installed the WebPack on two different machines.
Regards, Sietse Achterop Computing Science department University of Groningen
PS. I use this design in a number of courses on our University.
=============================================================== The VHDL RAM descriptions, see geheugen.vhdl, are like:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
entity mc8051_rom is
port (clk : in std_logic; -- clock signal reset : in std_logic; -- reset signal rom_data_o : out std_logic_vector(7 downto 0); -- data output rom_adr_i : in std_logic_vector(15 downto 0)); -- adresses
end mc8051_rom;
architecture behav of mc8051_rom is
- we use a RAM that is initialized via data2mem with the hexfile. type rom_type is array (16383 downto 0) of std_logic_vector(7 downto 0); constant extrom : rom_type := (16383 downto 20 => x"01",
-- using 4Kbyte works?!
-- type rom_type is array (4095 downto 0) of std_logic_vector(7 downto 0);
-- constant extrom : rom_type := (4095 downto 20 => x"01", 19 downto 6 => x"00", 5 downto 0 => x"23" ); -- to avoid optimalizing out? Needed?
signal rom_adr : std_logic_vector(13 downto 0);
begin rom_adr