Hi,
I have a design, where I want to interface an ADC (250 MHz) to a Spartan-3E.
The clock from the ADC enters the FPGA via LVDS, gets IBUFGDSed and enters the DCM. It leaves the DCM as CLOCK_0 and half the inputclock, CLOCK_DV. CLOCK_0 then clocks a IP-Core FIFO.
Meanwhile, the DATA from the ADC (LVDS as well) enter the FPGA and are routed into the 8-bit input of the FIFO. There I want to be sure, that the DATA are valid, 0.92ns (!) before the rising edge of CLOCK_0.
How can I constraint this? OFFSET does not work, because it just constraints clocksignals from the pads. I noticed, that the translator creates "TS_dcm1_CLK0_BUF" and "TS_dcm1_CLKDV_BUF" with the appropriate periods (4ns and 8ns) for the signals behind the DCM. This is very nice, but I can't refer to these clocks before the compilation.
Furthermore, how can I reach my goal? I will try to use a phase-shifted clock on the DCM, but how can I control if my constraints are met?
Any help is greatly appreciated, since the Help-Section concerning Constraints on xilinx.com is down at the moment. I'm using ISE Webpack.
regards, Christian