OFFSET and Data Clock Skew?

Hello,

I'm trying to register some data coming from an ADC at 4ns period. I currently have the following in my UCF:

NET "adc_clk_p" TNM_NET = "TG_adc_clk_p"; TIMESPEC "TS_adc_clk_p" = PERIOD "TG_adc_clk_p" 4 ns HIGH 50%; NET "adc?_db_p" OFFSET = IN 1.0 ns BEFORE "adc_clk_p"; NET "adc?_db_n" OFFSET = IN 1.0 ns BEFORE "adc_clk_n";

However, the adc data arrives 2.59 ns +- (jitter) after the rising edge of the clock. Is there anyway I can specify this in the TIMESPEC? The PHASE attribute of TIMESPEC appears to only be valid for clock relationships, correct?

I meet the constraints just fine, but when I inspect the registers in chipscope, the adc output looks noisy:

formatting link
(time domain)
formatting link
(freq domain)

Here's the output from Timing Analyzer:

================================================================================ Timing constraint: COMP "adc1_db_n" OFFSET = IN 1 ns BEFORE COMP "adc_clk_n";

1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 0.824ns.

-------------------------------------------------------------------------------- Slack: 0.176ns (requirement - (data path - clock path

- clock arrival + uncertainty)) Source: adc1_db_n (PAD) Destination: adc1_iface/ibuf_out_r_0 (FF) Destination Clock: adc_clk rising at 0.000ns Requirement: 1.000ns Data Path Delay: 1.389ns (Levels of Logic = 2) Clock Path Delay: 0.745ns (Levels of Logic = 4) Clock Uncertainty: 0.180ns

Data Path: adc1_db_n to adc1_iface/ibuf_out_r_0 Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tiopp 1.206 adc1_db_n net (fanout=1) 0.000 adc1_iface/ array_gen[0].diffend_gen.ibufds_inst/SLAVEBUF.DIFFIN Tiodi 0.000 adc1_iface/ array_gen[0].diffend_gen.ibufds_inst/IBUFDS net (fanout=1) 0.054 adc1_iface/ibuf_out Tidock 0.129 adc1_iface/ibuf_out_r_0 ---------------------------- --------------------------- Total 1.389ns (1.335ns logic, 0.054ns route) (96.1% logic, 3.9% route)

I believe I want adc_clk rising at 0.000 ns to be adc_clk rising at

4.0-2.59 ns = 1.41 ns?
Reply to
Brandon Jasionowski
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without being any expert on the topic, have you considered that bad PCB layout (ground bounce, crosstalk, too long traces, no termination and so on) might be the cause of the noisy data? PCB layout is very important at high frequencies > 25Mhz and with fast risetimes.

Reply to
kislo

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