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NV on-chip memory?

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It does not direct relate to the NV aspect, but Paul was talking about the SRAM contained in an FPGA. So I throwed in my larger SRAM wish. For code memory I'm happy with larger serial Flash chips when I can access them from the FPGA. Here the pin count is not so problematic and I know Flash integration is problematic from the technology point.

Martin

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Martin Schoeberl
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This Code-Ram should also be able to be Wide path and split, so that multiple cores can be supported, with wide opcodes if desired.

Given the relatively high Static Icc now of FPGAs, it would also make sense to look at Self-refresh DRAM - DRAM is much more die efficent.

Serial 'Data Storage' Flash is getting better all the time, and could serve as code memory in some instances. 'Jumps outside the Cache' would be relatively costly, but the streaming speeds are getting quite good.

-jg

Reply to
Jim Granville

about

Now you are opening the the wish list to this SRAM block. Perhaps that's one problem for such a feature. If A & X would integrate such a block they have to satisfy too many diverse requests. However, you can implement different interfaces to this block (split, multi port) by your own logic with multi-cycle access.

This would make the usage of the RAM more complicated. You have to account for the busy cycles introduced by DRAM refreshing. And AFAIK DRAM is a little different process that 'standard' cmos.

I would generally copy the code into the RAM befor execution. With an on-chip RAM you could perhaps abandon the instruction and code cache.

Martin

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Reply to
Martin Schoeberl

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