Number of taps for a FIR

Hello all,

I am planning to introduce a decimation filter in my FPGA design in order to reduce the sample frequency by 8. This has resulted in a 61 tap FIR filter. -It seems awfully large. Basically, I am asking , for an FPGA implementation, what is a REASONNABLE number of taps for a FIR filter?

(I am planning to again filter the decimation filter's output with a cascaded structure of 4 2nd order IIR filters. In my opinion it is that cascaded structure which is doing the REAL filtering and it happens to be smaller and more potent. It seems a shame to ruin the compactness of the filter modules with a huge decimation filter. P.S I have yet to implement anything; I am just doing the planning of the required modules for the moment so I may be completly off base in my previous statement)

-Roger

(Filter parameters, in case they are of interest : Normalized Passband=0.015 Normalized StopBAnd=0.062

60dB stopband attenuation 0.1dB passband ripple Sample frequency=1MHz 10 bits or 16 bits databus, don't know yet
Reply to
Roger Bourne
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Roger, Look at making your filter as a series of half-band FIR filters. These are efficient in that every other tap is zero. (Nice and easy to multiply by zero!) Use three, decimating by two at each stage. Your implementation should be a lot more compact. The later stages will probably have more taps, but the sample rate will be reduced, possibly allowing you to use distributed arithmetic. Cheers, Syms.

Reply to
Symon

Also, check out CIC (cascaded integrator comb) filters? Although 8 may not be a high enough decimation factor to make this method worthwhile. Cheers, Syms

Reply to
Symon

And keep in mind that when you decimate you don't need anti-aliasing at Nyquist (1/4 samples), you only need it at those frequencies where the energy is going to get through your IIR filters -- I see needing a

3-stage CIC filter to do this, which with a boneheaded implementation only requires 24 taps.
--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/
Reply to
Tim Wescott

As Symon indicated, you should look into multi-rate filtering. Basically, decimate by 2 in 3 stages. Each subsequent stage works at half the data rate, and the length of the earlier filters needn't be as long as the later filters.

That said, 61 taps is not outrageously long, (although by using multi-rate, you'll be able to at least reduce the sample rate of your longest filter). There is a paper by Goodman and Cary from the 70's that details a set of small half-band FIR filters (half the coefficients are zero) for decimating in multi-rate systems. Also, the decimating filter sections can be reduced using polyphase decomposition so that the filter sections run at the output sample rate rather than at the higher input sample rate. That sample rate reduction also allows you to make the filter physically smaller by using more than one clock per sample. The Goodman-Cary F8 filter is a 15 tap filter that has 5 unique non-zero coefficients. Through symmetry folding and polyphase decomposition, and using distributed arithmetic, filter breaks down into a 4 tap filter and a constant multiply added together, and it provides about 65db stopband attenuation and a reasonably steep transition. You'll have to work through the chart for you application, but you'll probably find you can use something like and F3, F5 and F8 filter in cascade to get attenuation in the aliased part of the stopband and a flat response in your final passband.

A CIC filter would probably not buy you much here, as it basically takes the place of the F3 filters in the early part of a decimation chain as far as response curve goes. Where your total decimation is only by 8, the CIC is probably not going to buy you anything. CIC comes in really handy is where you have either a high decimation ratio, or a decimation ratio that has to be programmable.

Your stated sample rates are actually quite low for an FPGA. You can easily run the FPGA clock at around 80 MHz without any special design considerations and do the whole filter serial, sequential or serial-sequential at a considerable area savings. (serial would be using distributed arithmetic, in which case you need a 16x clock, sequential uses one multiplier to multiply and accumulate several taps: basically timesharing the hardware). You may also find a FIR filter implementation for your final filter may be easier to deal with than an IIR implementation because you can generally getr by with far fewer data bits and the response is not subject to limit cycles and instabilities caused by finite precision of a fixed point implementation.

Reply to
Ray Andraka

I am new to the digital filter world. Every day I discover a new type another type of digital filter, so perphaps (or most probably) I am wrong in my following observation:

How can a half-band FIR filter be employed as a decimating FIR filter for a downsampling factor of 2 ? If my limited understanding of half-bands (Lth-bands=2) is accurate, then the stopband of the half-band will lie above Fs/4 (Fs/2 -Fpass, where Fpass cannot exceed Fs/4). This will violate the anti-aliasing criterion and as such will make it non-viable to use as a decimating filter.

What am I missing? (From what I can tell from Mr.Google, halfs-bands are very popular, so my reasonning must be off...)

-Roger

Reply to
Roger Bourne

Hi Roger, So, a lowpass half-band filter has a passband

0 to Fp where Fp is < Fs/4

The stop band is

(Fs/2 - Fp) to Fs/2

If you use this as your specification for a filter using the Remez exchange algorithm for making odd order (i.e. odd number of coeffs) FIR filters, you'll find every second tap is zero, except for the middle tap which is

0.5. (Unless you've scaled things somewhere)

To decimate by 8 in three stages, your first filter has a passband from

0 to Fs/32

and a stop band from

Fs*15/32 to Fs/2

As you're decimating, you can throw away every other sample that comes out of this filter. Then, at your new sample rate, which is half the previous rate so F2s = Fs/2 , your next filter has a passband from

0 to F2s/16

and a stop band from

F2s*7/16 to F2s/2

....and so on for the third stage.

Anyway, I hope this helps, I know my posts often ramble a bit, hopefully you can google some of this to make more sense! It works great though.

Cheers, Syms.

p.s. You could google for scopefir, a FIR design program that you can use for free for a while before you buy.

p.p.s. I guess you've been here

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Reply to
Symon

Roger, The book I learnt all this from is

Multirate Digital Signal Processing by Ronald E. Crochiere, Lawrence R. Rabiner

HTH, SYms.

Reply to
Symon

Hi Symon,

If the stopband is Fs*15/32 to Fs/2, then it implies that the attenuation at frequencies around Fs/4 will be rather weak. Isn't important that all frequencies above Fs/4 suffer a strong attenuation, in order the Nyquist criterion be met at the post-decimation sampling frequency (F2s=Fs/2) because we are downsampling by 2 ? (I get the impression the solution is staring me rigth in the eyes and I just can't see it! ;) )

P.S I been using ScopeFiR.

-Roger

Reply to
Roger Bourne

Roger, yes, as you point out, when the half band is used for decimate by 2, half of the transition band folds back on the other half of the transition band, so there is some aliasing in a band equal in width to half the width of the transition band. This folded energy is all adjacent to Fs/4. This happens because the half-band filter, by definition, has a symmetry about Fs/4, which means the attenuation is exactly 6dB at Fs/4.

If this is the only filter in your design, then, yes this would present a problem for decimation. The piece you are missing is that these are used in conjuction with other filters in a system, and the other filtering removes the energy left over in the transition band. Most of the time, you have one or more cascaded decimate by 2 half band filters, followed by a filter at the lower sample rate that does the final passband filtering. Each half band stage eliminates the aliased transition band left over from the previous halfband stage, and then introduces a bit of aliasing from its own transition region. The (typically last) last filter in the filter chain is not a half-band filter and has a passband that eliminates the transition of the last halfband filter.

Reply to
Ray Andraka

Ah, OK, I see your problem. The idea is that you keep (only) your band of interest un-aliased. When you're decimating, signals alias or fold back. What you do is decide all your signals of interest are in a certain band, say 0 - Fs/32 in my previous post, and make sure this band stays un-aliased. It doesn't matter that other frequencies get aliased, you can filter them out later at your lower sample rate! HTH, Syms.

Reply to
Symon

Ah, I see Ray's posted a good explanation! Thanks!

It's difficult to explain this on a text newsgroup as you can't see me frantically arm waving! So check out:-

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For some diagrams which show the aliasing when using CIC filters. The half=band thing is much the same. HTH, Syms.

Reply to
Symon

I get it now. The halfband by 2 filters do not (can not) remove the aliasing that is incurred by the folding of their transitions over Fs/4 (and are not intrested to do so...). However, we (the general WE) do not care that aliasing occurs, since the aliasing does not affect the frequency range of interest (0Hz to Fs_orig/(something rather big, at least 2 digits). The aliasing is OF COURSE removed by an additional filter (following the cascaded half band filters) which targets the bandwith of the data. Hence, the benfits of using a cascade of half band filters to decimate by a power of 2, as I understand it, are:

  1. Since aliasing is permitted (as mentionned before), the filter does not have to be sharp, and as such has a low nb of coeffcients.
  2. Since every other coefficient is 0, in HW implemention, the FIR will require only ~1/2 the amount of delay elements clocked at half the input sampe rate (of that particular half band).

Rigth?

-Roger

Reply to
Roger Bourne

Roger Bourne wrote: Hence, the benfits of using a cascade of half

Close. You have only half the mulitplies, since the multiplies by zero are trivial. Also, with the polyphase decimation, the filter gets split into two banks, each operating at half the sample rate of the input. One bank has all the even coefficients, the other has all the odd. Only one odd coefficient is non-zero, so the odd filter bank reduces to a constant multiply. Plus, that is the center tap; in most halfband filters, the center tap value is equal to the sum of the other coefficients, and is half the DC gain. As a result, that tap multiplier is frequently just a shift and a delay of half the filter length (this delay is an odd number of clocks). The delay for the other taps can either be half the length clocked at the output frequency, or the full length clocked at the input frequency, since only every other tap is used. The big savings is eliminating the multipliers.

Reply to
Ray Andraka

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