Hello all,
I am planning to introduce a decimation filter in my FPGA design in order to reduce the sample frequency by 8. This has resulted in a 61 tap FIR filter. -It seems awfully large. Basically, I am asking , for an FPGA implementation, what is a REASONNABLE number of taps for a FIR filter?
(I am planning to again filter the decimation filter's output with a cascaded structure of 4 2nd order IIR filters. In my opinion it is that cascaded structure which is doing the REAL filtering and it happens to be smaller and more potent. It seems a shame to ruin the compactness of the filter modules with a huge decimation filter. P.S I have yet to implement anything; I am just doing the planning of the required modules for the moment so I may be completly off base in my previous statement)
-Roger
(Filter parameters, in case they are of interest : Normalized Passband=0.015 Normalized StopBAnd=0.062
60dB stopband attenuation 0.1dB passband ripple Sample frequency=1MHz 10 bits or 16 bits databus, don't know yet