not clear about doing power estimation using xpower

hi, i am trying to do power estimation for xilinx fpga and decided use the xilinx xpower.i am not sure about how to fill in the toggle rate, the capacitive load,dc load during power analysis. i did look up the tutorials, but then i couldnt understand it clearly.can anyone explain to me how to go about? thanks dv

Reply to
savdeep
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for toggle rate, you have to make an educated guess based on your knowledge of your design. bit serial tends to have high toggle rates

50% or more. parallel arithmetic is quite a bit lower. For something that is a parallel data path design with no time multiplexing, something bewteen 10 and 20% is a fair shake.

For capacitances, you'll have to look at what you have connected to the FPGA.

Keep in mind that the web calculator is little more than an educated guess. I don't consider it more accurate than about +/-12dB. A huge factor is the routing and number of pipeline stages between registers... I've seen papers that claim as much as 30% power savings by going from minimally pipelined to single level of logic between FF's, and that is all just energy dissipated due to propagation of switching transients thru the routing and fabric. Keep in mind that most of the FPGA is routing resources, not logic, so trying to do a power analysis based just on logic is going to incur a large margin of error.

The bottom line, is that the web tool is only an estimator. Given the wide error margin, even that title is generous. That said, it still appeases those who push for power estimates.

The full up xpower based on simulation vectors is far more accurate, but even that is dependent on your simulation vectors being representative of the real operation, and it still includes a healthy error allowance for the statistical worst case part.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Reply to
Ray Andraka

I see three distinctly different purposes for a pre-design power analysis:

  1. You want to estimate battery life and required battery size, cost, and weight.
  2. You want to install the appropriate Vcc regulators, definitely not too small.
  3. You want to estimate thermal conditions, especially junction temperature.

#3 is the toughest, since it allows the least margin. If you have to design for 50 degr C ambient, and want to keep the junction temperature under the specified 85 degrees C, you are walking a fine line. Without a heatsink, you never get below 10 degrees/W, which means 3.5 W is your max limit. With a good heatsink and plenty of airflow, you can tolerate far more power, but with modern high-performance circuits you will always be close to the edge. Which means you estimator has to be accurate. An answer of "somewhere between 5 and 10 W" does'nt help you much, and "somewhere between 10 and 20 W" is even worse. Power consumption is a very important issue. You should forgive us for our relentless attacks on our competitor Altera. In many cases, the part with the guaranteed lower power consumption wins, and it is worthwile to explore all the advanced design methodologies in order to reduce power. Virtex-4 helps, if you are willing to use its power-saving options, like DSP slices, FIFOs etc. Modern FPGAs are not just seas of LUTs that you simply throw VHDL at. It pays to do some creative thinking and planning, if you want to avoid the power=heat crunch.. Peter Alfke, from home.

Reply to
Peter Alfke

I generally agree with your input Peter: power consumption is increasingly important, good estimation tools are critical, and advanced design methodologies are helpful. The relentless attacks on Altera would be more interesting if they better aligned with reality. Those customers interested in optimal power estimation accuracy will find compelling advantages with Quartus II support for Stratix II. Previous post (from Austin) highlighted accuracy of Xilinx estimation tool at +/- 50% - our correlation analysis indicates that this "accuracy" rating is exceedingly generous. Quartus II estimation tools provide accuracy +/- 20%.

I'll assume someone is thinking (as I agree again with Peter's assertion that Xilinx has been consistent in their messaging): if Xilinx says they are 10X better in power, better estimation tools don't really matter. Reality is that Virtex 4 static power is a little lower than Stratix II static power and Stratix II dynamic power is a little lower than Virtex 4 dynamic power. And both Altera and Xilinx can identify plenty of "ideal" design examples that make our respective parts look great and our competitor's parts look terrible. Design dependency becomes the limiting factor, and this of course is where tool estimation accuracy can be a critical factor.

If static power is really the limiting concern, then it is unlikely that Stratix II or Virtex 4 will be the ideal solution. Low-cost (albiet lower performing) FPGAs provide the lowest static power. Cyclone II has the lowest dynamic power of any FPGA and the lowest static power of any 90 nm FPGA, resulting in the lowest total power seen by an FPGA of this density.

Dave Greenfield Altera Market> I see three distinctly different purposes for a pre-design power

Reply to
Dave Greenfield

Dave,

For the record, I was referring to the Excel spreadsheet 'accuracy'.

Use of the verilog test bench file with the XPower tool results in a far better estimate, given the customer actually has captured what is really happening in their simulation.

As for your other claims regarding S2, I respectfully disagree.

As for Cyclone II, it may be that you have very low power (static).

We also sell the a static power versions called Spartan 3L.

But, have you fixed the power on surge problem in Cyclone II?

Aust> I generally agree with your input Peter: power consumption is

Reply to
Austin Lesea

We've checked XPower's accuracy, and it is much worse than +/-50%. I agree it should be significantly better than the web tool, given that it knows the placement and routing, and is connected to a simulator to get good toggle rates. That leads me to expect a very large error bar on the web tool.

There is no power-on surge on Cyclone II.

Interestingly, Xilinx's web site does not claim there is a power-on surge for Stratix II anymore, nor does it claim any power-on surge for Cyclone II. It appears that your marketing folks have removed their earlier claims related to power-on surge, presumably because they are easily contradicted by a lab measurement.

Vaughn Altera [v b e t z (at) altera.com]

Reply to
Vaughn Betz

Vaugn,

Page 3, lists a number of "in-rush" requirements.

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I won't bore you with listing all of your other power supply partners web site links all listing power on surges.

And, XPower requires you have a test bench of transistions for your design. I suppose you worked really hard to verify that your test bench was accurate? No, I suspected not. Maybe you designed a single 16 bit counter in an LX60 part? Easy ways to misuse all tools. Don't bore me.

Post when you have something useful to say.

And if there is no in-rush (power on surge), then straighten out your seven plus vendors collaterial. Not to mention your own collaterial.

Aust>>For the record, I was referring to the Excel spreadsheet 'accuracy'.

Reply to
Austin Lesea

And lists no In-rush for Stratix II, which makes sense given that there is none. This datasheet does not yet include Cyclone II, hence it has no statement about in-rush for it. As I said earlier, there is no in-rush for Cyclone II either.

Yes, we worked hard to make good test benches, and no, we didn't use a single 16-bit counter. We measured 9 designs, and compared dynamic power prediction accuracy vs. silicon. XPower had >20% error on all but 1 design, overpredicted power by up to +190%, and underpredicted by up to -90%. We used the same circuits and test benches to test the PowerAnalyzer in Quartus II, and its predictions were always within +/-20% of silicon.

Vaughn [v b e t z (at) alteara.com]

Reply to
Vaughn Betz

These little arguments between Altera and Xilinx can often be entertaining and informative, but sometimes they get a bit repetitive. As far as I have ever read, there has been no "in-rush" issue with Cyclone II or Stratix II devices. There apparently was some in-rush on some engineering samples, or at least there was the *possibility* of in-rush, and thus Altera had their worst-case specs set according. Altera says they don't have in-rush, and power-supply manufacturers like TI say they don't have in-rush. So could you please either drop this line of attack, or provide Altera and their users with actual evidence of this "problem" ? There are enough issues for which Xilinx chips provide a real and tangible advantage over Altera chips for you to concentrate on them - the "in-rush" claims smack of FUD, which is not becoming of you.

I've also looked at the in-rush values quoted for the original Cyclone and Stratix devices (being a user of both). Frankly, it's not an issue

- you'd have to have a design running under worst-case conditions and with a practically empty chip before the size of the in-rush current becomes an issue compared to the run-time current of the device.

David

Reply to
David Brown

Relax guys, it is both a dessert topping AND a floor wax!

Sheesh, you guys are like my kids always needling each other trying to get a reaction. Both of you have good parts!

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Reply to
Ray Andraka

Ray,

You are correct, Ray. We may disagree about who makes the "best" part, but it is the customer who ultimately decides.

Austin

Reply to
Austin Lesea

"Austin Lesea" schrieb im Newsbeitrag news:d8c9nv$ snipped-for-privacy@cliff.xsj.xilinx.com...

what to buy. But this doesnt neccessarily mean he buys the better part. The market leader isnt always the technology leader. But who cares about technology when your paycheck is top? But this is getting a little bit too philosophic, isnt it ? ;-)

Regards Falk

Reply to
Falk Brunner

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