Non-volatile FPGA in a small package

I am looking for my usual FPGA in a small package. This is a contract design and the customer has a preference to avoid BGAs. The only leaded part that will fit the board is a 100 pin TQFP. I found a couple of MAX II devices in this package and Lattice has some MACHXO parts as well as one XP part. Of the three, I like the XP better as it has 3000 LUTs to work with as well as PLLs.

Lattice also has an XP2 line which should be lower cost/higher density as well as lower power. But they don't seem to be available yet. I don't see stock on any parts and it looks like they are not supporting the TQ100 package.

I also wanted to consider the Xilinx XC3S-AN parts. The combinations of device and package are very limited with a one to one relationship. Each part comes in a different package and *only* that package. So there is no chance to upgrade to a different density part once you design the board. Of course, I don't think this is a real issues for this app, since any of the FPGA types are well large enough. But I also can't find any pricing. The other parts are all in the $10 - $15 range. I have no idea if the XC3S-AN is in that same range.

So does anyone know if the Lattice XP2 and the Xilinx XC3S-AN parts are ready for prime time? Should I skip these parts and go with one of the other choices? BTW, the customer has experience with the Altera parts and can already program them in system. So that is a definite plus for the MAX II. But it is otherwise at the back of the field with the least available LUTs and no PLL. So I really want to use a different part.

Reply to
rickman
Loading thread data ...

Hi Rick, Dunno if this helps, saw it in EDN yesterday.

formatting link

"High noon for FPGAs: Low-cost-versus- high-end showdown Greenhorns in the high-end-FPGA market, Lattice and Actel are shooting it out against old hands Xilinx and Altera in the battle for low-cost devices." HTH., Syms.

Reply to
Symon

Missing from the 'usual suspects' list seems to be Actel ?

I see their IGLOO series offers both VQ100 and QFN132 ?

VQ100 (14 x 14 mm) 79 71 71 68/13 QN132 (8 x 8 mm) 81 80 84 87/19

-jg

Reply to
Jim Granville

The Spartan-3AN family recently went into full production, with the XC3S50AN release imminent. I would say that they are ready for prime time. Pricing is definitely in the same range, partly as a result of the very limited package options - see the press release from the announcement, which notes a sub-$5 price for the XC3S200AN

formatting link
Or you can get a Spartan-3AN Starter Kit with an XC3S700AN for only $225
formatting link
Unfortunately it takes a while to get pricing and availability onto distributor web sites, but that will come soon.

Marc Baker Xilinx

Reply to
Marc A. Baker

Hi Rick,

Just wanted to let you know that XP2-5 engineering samples are available now (and the FPGA should be in production by the end of the year). TQ100 package isn't supported though, however if your customer will agree to change the anti-BGA preference there is very small 132 pin csBGA package (8x8 mm, only three rows of pins going around the perimeter) available.

Alex

Reply to
Alex

Ok, that is good to know. But I still don't have any idea of the price. I would have thought that these parts would be a bit cheaper than the XP line, but it looks like the smallest member of the family is a bit bigger than in the XP line and has a lot more features. So I don't know if it will be any cheaper and may actually be a lot more expensive since it only comes in packages with higher pin counts. I know that price correlates very strongly with I/O count.

Other than the issues with customer confidence (he had a bad experience with Lattice tools once) either the XP or the MachXO line seem to provide the most flexibility. The XP is a lot larger and has the PLL that I might need. The MachXO uses the TQ100 package for all four device sizes and the two largest also have a PLL. The one advantage of the Altera chips is that they appear to support a user flash memory while the Lattice parts don't seem to have that. This is not a show stopper, just something to note.

Looking at the tools, it is not clear to me if I can really evaluate them using ispLever Starter. This package seems to not include the full set of tools including the simulator and programmer. So I can't actually program a device with the starter tool, right? Is the simulator that comes with the ispLever package limited in any way? The web site does not describe it very well.

Reply to
rickman

Thanks for the info. If the XC3S50AN is not even in production yet I am not so sure I am ready to use it. Xilinx does not have a good reputation for making parts available to the masses in early production, much less preproduction. Besides, I still have no idea how much it will cost. Saying it is $5 in qty 250,000 would make me think I could get 100 at $10 each, but past experience has shown it can be anywhere North of $20 instead. That would not be very competitive.

One thing Xilinx has in its favor is the reputation of the tools. Even the web pack version seems to be pretty good.

But the skids are greased for Altera with the customer already having support for programming them in-system. Too bad the MAX II parts are not the first choice technically.

Reply to
rickman

As long as Digikey doesn't carry them, they are not ready...

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
 Click to see the full signature
Reply to
Uwe Bonnes

No simulator but programmer is there. As for a hardware they offer a cheap parallel and pricey USB programmer. I've used ispLever Starter in several projects IMHO it is a good tool.

Regards, Maki

Reply to
Maki

Searching em.avnet.com shows XC3S50AN-4TQG144CES at $14.89 - no stock of course, but "they say" 4 week leadtime. I believe that's a notional 1-off price (no: "buy qty 22") so 100-off is likely to be closer to $14 than $5.

As for development, you can presumably use the equivalent XC3S50A part ($12, for the -I grade, 16 in stock) to get started, and move to the -AN when they appear. (Xilinx wouldn't make the pinouts incompatible, would they? :-)

- Brian

Reply to
Brian Drummond

Thanks, I had searched there, but I forgot to check "Search All Items" rather than just stock. I'll take a look for the 256BGA.

Reply to
rickman

HI Rick,

I don't know where you are based, but there is a company in Germany

formatting link
that sells an XO-640 starter kit for something like ?75. This kit can be used as USB based programmer too (it has all the pins available to the outside world).

I've seen prices for the XP2 (5K LUT) in T144 package for less then $10 in normal quantities.

Besides - I've made a 50x50mm board with this device on it, got my ES silicon pretty fast. This board has about 50 pins to be uses as a mezzanine board.

Best regards,

Luc

Reply to
lb.edc

You can get a 60 days evalution for full ispLever tool including Modelsim for Lattice (without any performance limitations) it, probably, will cover the time-frame you'll need.

Alex

Reply to
Alex

You might find that Actel suits your needs ...

formatting link

(It looks as though Actel carries some smaller ProASICPlus parts in a TQFP 100 package. Those parts have 2 PLLs and are Flash-based [reprogrammable, immune to SEUs, etc.].)

K.

Reply to
Kryvor

But if there is no simulator, how can you really do anything useful with the Starter kit? If you just want to play with the software it would be fine, but if you really want to evaluate the package, you need to do a small project which requires a simulator, no? I just don't have the time to spend playing with tools other than for a project of some sort. My customer told me he tried the Lattice parts once and had a problem using the tools, so I would want to give them a thorough going over and still be prepared to switch to a different brand of part if the tools proved wonky.

In another thread early this year, I was reading that the parallel port has gone they way of the dodo bird (at least on laptops) and none of the alternate parallel port solutions really work reliably. So I want to avoid them at all costs. I'll look at the USB programmer. I haven't had a chance to read up on programming the little buggers. Do these programmers work through the JTAG port on the parts?

Reply to
rickman

The Flash cells may be imune to SEUs but the active logic certainly isn't. SEUs "tend" to be noticed in SRAM cells first but registers are also affected by the same radiation for FPGAs of any flavor as well as ASICs and other standard parts.

- John_H

Reply to
John_H

I use external tool for simulation and an USB programmer. Yes programmer uses JTAG or slave serial.

Regards, Maki

Reply to
Maki

It's not free, but the full ispLever software is not expensive and includes branded ModelSim similar to the Xilinx ISE offering. If your starting from Altera tools rather than Xilinx, you may not find the ispLever quite as familiar. Those of us coming from the "X" world can see the common roots of ISE and ispLever from NeoCad. Even the file extensions are (mostly) the same.

I have also had issues with ispLever, but I am fairly happy with the 6.1 version, and I understand 7.1 is better, but I haven't upgraded yet. ispLever also includes a choice of Synplify or Precision for synthesis, so if you're comfortable with one of these already you can get a running start.

As for the quad flat packs, I would not recommend using them for high-speed designs that may be sensitive to ground bounce. I had trouble with ECP2-6 parts (similar to XP2 but no flash) in the TQ144. The designed used a 7:1 deserializer (Channel Link) and had trouble locking when other unrelated outputs were switching. I got the design to run by using slow slew rate on outputs, but couldn't do everything I wanted with it. I have a new design with the same part in the 256-pin BGA and it is very stable even with a lot of fast switching and two 7:1 deserializers. Since you mentioned PLL's I thought you should be aware of this sort of package issue even if you don't need to run particularly fast.

Regards, Gabor

Reply to
Gabor

Yes, however there's a big differnece between developing for these vs. Altera or Xilinx SRAM parts: the toolchain is less integrated and thus much slower, and the programmer is outrageously slow and pricey for what you get. If you are used to fully integrated toolflow, and to doing fast test downloads during development, this can be quite aggravating.

It also seems that you can't get pullups on inputs, and instead of merely being cautioned against using non-clock inputs as clocks, you literally can't do it - meaning board designs with stupid mistakes that might be programmed away with other devices are more likely to require modifications with these.

On the other hand, if you prefer to do everything in simulation and not make incremental trials in hardware, and you value synopsis over X or A's tools enough to habitually use it anyway, then maybe these parts are just your thing.

Reply to
cs_posting

You can't use clk input buffer on non clock input pads, but you can use any input as feed for the internal clock buffer (GLint) to drive the clocks from any input you like. The perfomance may be much better, when using the clock pads, but you are not limited.

You can use Synopsys for synthesis of any fpga, but I guess, you get not very good results when using it for ram or flash based Fpgas. Even for Actel fuse based fpgas you need to check, wheter you get better results with Synopsy or Synplify. I used both synthesis tools for serveral flash based designs and learned, that I gained sometimes 10% with the one and sometimes with the other tool (depending on the design).

bye Thomas

Reply to
Thomas Stanka

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.