Non-project mode Vivado simulation?

there are two ways: you can use xvlog and xsim or you can use vivado -mode tcl -source foo.tcl

with a foo.tcl which has: create_project -force foo_proj_1 add_files bar.v run -all

The sec> Is it possible to run a Vivado simulation in non-project mode?

Thank you for your reply.

I thought these were available as Tcl commands within Vivado. But I guess xvlog/xvhdl, xelab, and xsim will do what I was looking for.

The latter was a project mode script, even though the project overhead seem to be minimal. Again, I think xvlog/xelab/xsim will do what I want.

Best regards

//Petter

Yes, it's fairly easy using xvhdl, xvlog, xelab and xsim as described in UG900.

For an example, I have a SPI Master module I've set this up for. I created a spi_master.prj file with the following contents:

vhdl work ../src/spi_master_ae.vhd vhdl work ../tb/stdtb_pb.vhd vhdl work ../tb/models/spi_bfm.vhd vhdl work ../tb/spi_testbench_pb.vhd vhdl work ../tests/spi_testcase_e.vhd vhdl work ../tests/spi_tc_a.vhd vhdl work ../tb/harnesses/spi_harness_pb.vhd vhdl work ../tb/harnesses/spi_harness_tb_e.vhd vhdl work ../tb/harnesses/spi_harness_tb_a.vhd vhdl work ../tb/spi_tb.vhd

I then run xvhdl using the following to compile everything:

# xvhdl -prj spi_master.prj

Next, I elaborated the design using:

# xelab work.spi_tb -prj spi_master.prj -debug all

Finally, I kick off the simulation using the GUI with:

# xsim -g work.spi_tb

UG900 provides much greater detail on the other options for each of those steps too.

The problem with command line tools is once you are in vivado gui, it is not possible to reload the files any more, one has to kill xsim. The overhead of an in memory project is extremely low and vivado know how to recompile the simulation.