Hello,
I was wondering if anyone knows if it's possible to perform a "non- intrusive" readback operation on the FPGA configuration data in order to verify its correctness and to ensure that it hasn't been corrupted (specifically for a Xilinx Virtex 5). Looking through the datasheet, I can find all the information required to DO a readback, but I can't seem find anything regarding whether or not it's intrusive.
Thanks a lot.
Pepi
Pepi,
The readback for all Xilinx FPGA's is non-intrusive by design.
It wouldn't be very useful if it wasn't.
The LUTRAM bits are marked as "volatile" by the programming software so that a readback of the CLB contains only that information that is intended to be static (not changing) so a compare may be done to see which bits have flipped.
There is a mask file which is also created by the programming software that marks all the commands and non-information bits so they are not part of the readback compare.
Note that the readback does contain the BRAM contents, and if the design is changing the BRAM contents, then those changes will show up as differences. You may intentionally mask out the BRAM contents if you are not interested in those bits changing (see app note below).
The application note:
Details how an IP core may be used to have the device check (and correct) itself. The BRAM may be excluded from this check (and correct).
This core is also useful for testing, as it may be used to inject errors. By injecting errors one can determine if the system you have is robust in terms of how it mitigates against failures (does it fail gracefully? and recover? does it meet what you intended?).
Austin
More,
The app note is for V4, but also applies to V5.
Austin
Aust> Pepi,
Hi Austin,
Thanks for your help...Greatly appreciated!
Pepi
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