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noisy rising edge clock - non-monotonic clock

We are having some tests failing under certain clock signals. The clock signal is generated in an external device with different drive strengths. The external clock is used to clock some Virtex2P internal FFs which outputs goes to the DUT. We tried different drive strength for the clock such as: 1mA, 2mA, 3mA, 4mA,and 6mA. The test only fails with 2mA drive strength. Analyzing the captured waveforms, we found that there are some ringing (non-monotonicity) in the 2mA clock at around 1V and 2V. Since we are using LVCMOS33. From the V2P data sheet, on page 76, it's stated that for LVCMOS33 VIL min = -0.2 VIL max = 0.8 VIH min = 2.0 VIH max = 3.45 Since the clock signal has a 'draw-back' (ringing) at ~1.0 and at ~2.0V, is that what actually cause the problem with the clock? On the other hand, I read on the xilinx's Answer Database, answer #

11308, that there is a transition point at Vcc/2 with a hyteresis of ~100mV and this apliable to both data and clock inputs. I was looking for more detailed information on the hysteresis (in X FPGAs) , but I could not find anything else. So, my first question: is Vcc/2 the 'real transition' point for the clock? for 3.3Vcc that point is at 1.65V. In my case the clock is clean and monotonic between 1.1 and 1.9. So, why should I have problem based on the Vcc/2 transition point? However, using the values from the data sheet, VIL min = -0.2 VIL max = 0.8 VIH min = 2.0 VIH max = 3.45 I see that the 'draw-back' happens very close to the borders, close to Vilmax and Vihmin, and could cause some problems.

I do understand that the non-monotonic clock can cause problem, but at this moment there no much we can do with the board. I'd also like to find any doc on Xilinx website related to the integrity of the clock signal. If you can point to me to some document that could clarify the behave of the FFs with noisy clocks, I'd really appreciate it.

Thanks,

Cris PS: the rise time for the 2mA is ~22ns

Reply to
csisterna
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Hi Cris, Your problem is probably the falling edge of the clock being seen by your cct as a rising edge...

...because you have a clock that is very slow. Really, very slow. You need to fix this, maybe with a Schmitt trigger buffer. HTH, Syms.

Reply to
Symon

Chris,

-snip-

Vcc/2 is the design center by simulation for perfectly "typical" process corners. In reality, this does vary. If the p is stronger, and the n is weaker (for example) the transition point is no longer Vcc/2.

Generally, CMOS varies from ~33%, to ~66%. The thick oxide devices are not so variable as the mid, or thin oxide devices, but 33 to 66% is a good guideline.

If you want to switch at a precise level, then you should be using a standard that uses the Vref input to the input comparatot.

If you can point to me to some document that could

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Your problem is incredibly basic, and is not uniquely a "clock" problem. It is just that having this problem on a clock signal can cause multiple problems.

You need to fix the signal integrity, as changing the threshold may fix this one board, and may not be what works for another board. The fact that changing the drive strength does little to affect the shape of the received signal implies that there is no match from the source to the line, to the load that will work. Often this is due to the line itself having a discontinuous impedance (it may have multiple drop off points, which means that series termination can never work -- parallel termination will only work in such cases).

You may wish to enable the parallel split DCI termination option in the IOB. You will need to connect the reference resistor pins to resistors to use this feature.

For V4:

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Also exists for V2, V2P, and V5.

Austin

Reply to
austin

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