No submodule instantiation as seen in FPGA Editor

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Hello,

I have a top level module for a XCV1000.  It has a following specified UCF
for the pin and netname mappings. I have instantiated to fo the DLLs and
two user modules.  The DLLs are the same as in XAPP132 for a 4X clock
signal generation.  When I generate the bit file and look at the design
with FPGA Editor, I don't see any signals or CLBs for one of the two user
defined modules.  There are some warnings about clock signals and I am
using "clock_signal" synthesis attribute to tell XST which are the clocks,
basically restricting the clocks and reducing the GCLK usage.  When I
comment out one of the modules that is instanitated all the time and
re-synthesize, I see module instantiation. I have put the files online
that I think may be helpful.  These files can be found at:

http://www.stanford.edu/~johnd/Xilinx /

The top level module is CP2_FPGA and I instantiate two user modules within
CP2_FPGA:

R3000Init1
Test00a

The R3000Init1 always shows up and Test00a doesn't. If I comment out
R3000Init1, then Test00a shows up in FPGA editor.  I have attached the log
files when I synthesize with both modules: R3KandTest00.txt and with just
the Test00a: JustTest00.txt.  The CP2_FPGA.ncd is the file for FPGA Editor
for the first case (both modules) and CP2_FPGA_last_par.ncd is the FPGA
Editor file for the latter case, when R3000Init1 is commented out.

I can include other files, but it is strange that the instantiated module
is not in the FPGA Editor with the related CLB's depending on what other
modules exist. I would like a highly modular design for easy of debugging
and code management.  Any idea's why the module doesn't appear in the
FPGA?

Thanks,
John D. Davis


Re: No submodule instantiation as seen in FPGA Editor
Found an issue with the Verilog module please ignore. However, it would be
nice if the Xilinx tools gave a big warning saying that nothing was
synthesized, placed and routed for module X...

Cheers,
JOhn

On Mon, 8 Aug 2005, John D. Davis wrote:

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John D. Davis
PhD Candidate
Computer Systems Lab            Office     # 1.650.723.6891
Stanford University            Fax     # 1.650.725.6949


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