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No more gate-level simulation. for Cyclone V !!!

Hello,

I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful.

Now using a Cyclone V I found that I can't do timing gate-level timing simulation, quartus does not generate the SDF file, the *.sdo file.

Altera/Intel says this on the documentation regarding simulation:

"Gate-level timing simulation is supported only for the Arria II GX/GZ,Cyclone IV, MAXII, MAX V, and Stratix IV device families. Use Timing Analyzer static timing analysis rather than gate-level timing simulation."

I don't even know how to interpret the last sentence, how does the Timing analyzer give me the same info / graphical view of the timings of the critical signals and buses that I'm trying to view ?

Any help ? Thanks.

Luis C.

Reply to
Luis Cupido
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Static timing analysis does not give you the same info as a gate level simulation. Static timing analysis is a far better way to verify your design for correctness compared with gate level sim.

Kevin Jennings

Reply to
KJ

One big problem with static timing analysis is that it doesn't have a means of verifying the timing constraints. You analyze your design, construct the timing constraints, but there is no way to even check for typing errors.

So if any of the constraints are too lax, your design will pass analysis, but can fail on the bench and there is no way to find the bug. Then a timing simulation can save the day.

But in general, static timing analysis is a much more comprehensive way to verify timing. It is not so easy to get information on how to fix the problem, but at least it points you to the problem.

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  Rick C. 

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Reply to
Rick C

That is not the issue, the issue is that Intel has decided to remove one of the tools we use to check our design.

Obviously if static timing fails nobody will run gatelevel simulation, however, if static passes and your design does not work (has happen to me and I am sure to others) then gatelevel simulation provide a valuable and easy to method to see where signals are "going red". Gatelevel is also useful to see what happens before reset is asserted.

Given that all other vendors provide gatelevel timing I failed to see why Intel in their great wisdom has decided to remove this feature for one(?) of its family.

Hans

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Reply to
HT-Lab

Maybe it's just me, but I hate saying "Intel" rather than Altera. :(

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  Rick C. 

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Reply to
Rick C

I have the same, occasionally I still say Actel instead of MicroSemi...eh...MicroChip. I don't think we have to take this so seriously as long after MicroSemi bought Actel you could still find "Actel" all over their documentation.

Hans

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Reply to
HT-Lab

I came across this a few years ago and I seem to remember that it was all f amilies from Cyclone V onwards so not just one family. Don't know if this h as changed since then.

Also from reading docs at that time Altera docs indicated the reason for no t supporting timing sim was because designs were getting so complex timing sim takes too long to be viable and so would be dropped. Interestingly when I checked the Xilinx docs at that time timing simulation was still support ed and their docs indicated because designs where becoming more complex tha t timing sim was recommended!! The polar opposite to Altera.

As I said that was a few years ago. I was working on a project where we had to do timing sim because it was part of the development process. That proj ect switched to Xilinx devices just because of this issue.

I haven't needed to do timing sim since so I don't know if much has changed since then.

Reply to
pault.eg

That's interesting the Altera took that tact. I wonder how much effort it really is to maintain the SDF generation - surely it's a solved problem?

On the other hand, I do find the need for SDF annotating, gate-level simulations as a waste of time, with better ways of accomplishing the same goals. I've not run a full timing simulation in probably over 20 years... In fact, even the need for gate-level simulations at all, is remote - like once a year or so - and these are almost universally to confirm/debug a vendor RTL/netlist mismatch...

So, I sortof understand Altera's thought process. But I do know there's certainly a vocal group of folks who insist gate-level sims (with or without timing) is a sign-off requirement. And Altera brushing off those folks doesn't seem like a wise move..

Regards, Mark

Reply to
gtwrek

Agreed. In fact, the last couple of times I remember running a gate level sim was to show a demonstrate an incorrect synthesis implementation...to Al tera. But to do that I only had to run the sim for a couple of clock cycle s or so. In at least one of the cases, I modified the design to bring out an external signal to a pin so that it could be directly observed to be inc orrect. The testbench was an instantiation of the source design in paralle l with the gate level sim.

Altera is correct from the viewpoint that running a gate level sim as a sub stitute for timing analysis is a waste of time and resources. However, fro m the viewpoint of having a way to validate correct synthesis (whether this is done routinely as part of company's design process or is an exception c ase) the gate level sim has usage.

Kevin Jennings

Reply to
KJ

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