On a project I am working on, I recently had the requirement of embedding an ethernet controller into the system. Since I already had a Cyclone on the board I decided to go with the approach of embedding a NIOS2 processor in the FPGA and adding the phy and other devices necessary to the board. At the moment, I am working on the considerations of how to interface this processor to the rest of the system which contains an Addr, Data, Control bus structure driven by a DSP. Almost all of the devices on the board are memory mapped and can be read or written to as a memory bus cycle. Ultimately, I would like to find a way to allow both processors to share the bus to access the IO devices as needed.
In order to do this, I believe I would need to implement some form of bus arbitration scheme that would look at which processor is attempting to use the bus and to assert back a wait signal if the bus weren't ready. From what I have read about the Avalon bus, it sounds as if this should be possible as I read something about variable wait states that can come from the peripherals. I am not certain how to implement these pins in the SOPC builder and I was wondering if someone could help me.
Ideally, the NIOS processor would be the bus slave as the DSP has a pin that can be asserted to request the bus from it. When the bus is granted, the DSP places all its signals in the high Z state and other devices can access the bus as desired. The reference documents show examples of putting multiple NIOS2 processors together with a MUTEX on the bus. Unfortunately, I am not certain how this would work with the other processor not being a NIOS2. Can anyone provide some suggestions of how to implement the needded functionality in the NIOS?