I am trying to understand the low level startup sequence on a custom Nios board. When the Nios (3.2) resets, what determines where it fetches its very first instruction? Is it always from the onchip bootstrap area or is this configurable? I don't have the OCI so I assume I can't just step thru from reset on my target (with gdb).
As I understand it, SOPC(4.0) compiles my custom bootstrap and Quartus (4.0sp1) adds this code to the pof, but not to the application srec. I am confused that the objdump for the bootstrap shows it is compiled for my SRAM base, not the onchip area. The Nios manuals say the code is not generally relocatable so this does not seem right. I don't see how to fix this base in the Nios dialog - it appears to be set correctly.
TIA