Nios II Going Live...

Interesting. Friends, what *is* this vaunted MicroBlaze interrupt latency (in cycles or ns)? Is there some special mechanism, or is it simply clean living?

(By the way, interrupt servicing (interrupt and return from interrupt) completes in as few as 6 cycles on the good old xr16 soft processor core.)

Thanks, Jan Gray Gray Research LLC

Reply to
Jan Gray
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Multiple embedded processors?

I built a Stratix design with 6 Nios' on it a long time ago. The design from start to finish took less than half a day. Could have been more if I had the space on the FPGA.

-- Pete

Reply to
Peter Sommerfeld

May I rephrase it, and make a question out ot it ? Are the any transputer loke-a-likes WORKING on an FPGA ?

Reply to
E.S.

Interesting question. I am giving some consideration to inserting my own cpu into an FPGA to be programmed in Forth. I remember the Transputer architecture and instruction set as being well suited to implementing a stack language as well as being rather minimal. But I can't find my copy of the instruction set reference manual. Anyone know where I can find a copy?

--
Rick "rickman" Collins

rick.collins@XYarius.com
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Reply to
rickman

It's a stack machine, but its model of how to use the stack is fundamentally different from Forth's. The stack is very shallow and must be *empty* at every branch! It's designed for expression evaluation in Algol-like languages, nothing more.

The Transputer's intended strength is very fine-grained multitasking: since it has almost no execution context to save, context switching is very fast. They were also fairly radiation tolerant, so they were used for some space applications. I'm sitting here watching telemetry from HETE-2, which has four T805 CPU's on board.

In general, I would not recommend the Transputer architecture for most applications. It basically combines the disadvantages of register and stack machines. Its ratio of instruction/data accesses is very high compared to other architectures, leading to serious inefficiency when running ordinary serial code.

-jpd

Reply to
John Doty

Not yet. Somebody else over in the Tp NG said they were going to clone the thing wholesale for code compatibility but didn't say how or when they would (a student I thinks).

Apart from me, I don't think anyone else has the inclination to try, most people probably have a job, and the Tp has had enough trashing to make alot of people stay away. And the complicated UK/US thing is there too.

The MT core I am working on will likely get Tp scheduling and message passing and more but it takes time. The core is only now running simple threaded codes. Today it hit 100M cpu cycles on 16threads (the same trivial code on all), but doesn't do much interesting yet till more opcodes implemented. Its only been 3+ months since I started. I have to go back and bring the Verilog back into sync with C RTL code too. There are some big issues up ahead like the cache & TLB design, sometimes MT helps alot, maybe not always.

Now I hope you'r not asking for a precise clone because as you must know, FPGAs don't clone anything well for which they were not originally intended for.

Anyway stick around to see posts on progress:)

regards

johnjakson_usa_com

Reply to
john jakson

The Transputer Instruction set is easy enough to find on the web, use google to find a few portals with all the links, like classic old comps, wotug, etc.

In c.s.transputer NG look for Ram and his home page and links, docs, even OS stuff. The ISA also has a compilere writers guide to explain it.

I never looked at it myself, never will, theres too many things I never liked about it, byte encoding, and mostly because there are just so many instructuions for what is supposed to be a simple cpu. later on the whole kitchen sink fell into it, graphics rendering and so on. Even related codes have odd hex codings, like they did a,b,c, x,y,x then realized later to put in d but right after z.

regards

johnjakson_usa_com

Reply to
john jakson

I just realised, you probably don't need to look at the Transputer because it has no sp type stack that you'd need for Forth, Pascal, C etc. It does have a HW stack for eval expressions just like a HP RPN calc but it is only 3 reg deep and tied into the scheduler for switching processes when its empty IIRC..

The reason of course is the same as HDL, do Verilog or VHDL allow you to write code that is stack based or implies recursion, no. Occam being parallel is more like a HDL, think HW and not seq stack scopes. For same reason I have no sp either. Infact although Occam allows functions IIRC it forbid recursion because the compiler had to know in advance how to lay out memory as much as youd floorplan cells. Functions can still work with out an sp but other memory management techniques are called for.

A google for Transputer & Forth should draw a blank I'd guess but I could be wrong.

Yes it does look like they did it, well I wonder what they did?

regards

johnjakson_usa_com

Reply to
john jakson

It could be done, but it wouldn't be efficient. You'd have to implement a separate software number stack.

-jpd

Reply to
John Doty

I did it, and it was pretty fast. The top of the stack was cached in the internal register stack and flushed to the workspace when full and in a few other cases.

Andrew.

Reply to
andrew29

It is not the stack (or a stack). These are registers at the lowest level, almost a RISC way to write microcode explicitly. The register at the next to lowest level are 16, and you can add two registers and put it back in a third by 3 single byte instructions. You can use a couple of those for stack pointers, without exhausting resources, like in a Pentium.

Of course you are wrong. You should know by now, that there is a Forth for every processor that is over 6 month old.

tforth is the precursor is iforth, and it is still available from DFW. It is a solid piece of work, if I may say so myself. There are more.

--
Albert van der Horst,Oranjestr 8,3511 RA UTRECHT,THE NETHERLANDS
        One man-hour to invent,
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Reply to
Albert van der Horst

Well people will find away to do whatever crazy thing they have in mind:)

regards

johnjakson_usa_com

Reply to
john jakson

Peter,

I was referring to hard IP uP, not soft cores.

Aust> Multiple embedded processors?

Reply to
Austin Lesea

Ofcourse I checked on the next line before signing off, and saw tforth and others

Reply to
john jakson

This is where we are today, but it just doesn't play to the strength of an FPGA. It's a bit like having one (or 8) block RAM. The FPGA really gets rolling when we can make parallel use of a shed-load of resources. Just as nothing can beat the bandwidth of a big FPGA with all the block RAMs going in parallel, nothing will be able to touch an FPGA with lots of application-tailored CPUs.

Not great for evaluating spreadsheets, but pretty good in other domains.

I once had a project (paper only) where each processor's instruction stream was scanned for the opcodes used, then the corresponding FPGA processor implementation was modified to match the usage.

Reply to
Tim

Surely spreadsheets are pretty much infinitely parallel once you've spread up the dependency graph for the cells among the various processors ... word processing is the bit I have more trouble thinking how to divide among a myriad processors, not that anyone types fast enough for that to matter :)

Tom

Reply to
Thomas Womack

^^^^

John, looks like you're most of the way there ;-)

I still don't understand why Americans shorten mathematics to 'math'.

Nial.

Reply to
Nial Stewart

I don't know either, but I think its because I don't ever hear the term arithmetic used in kindergarden level like we did in UK so math got pushed down to cover that and never got explained as being more serious term when they grow out of it. And where did all the u's go too:)

regards

johnjakson_usa_com

Reply to
john jakson

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