NI*S II-verilog in Virtex FPGA

NIOX features

- NI*S II ISA Compatible

- no pipeline

- no i/d cache

- barrel shift implemented

- interrupts implemented

- mul/div emulated by sw trap

synthesis results for Virtex-2 ========================================= Logic Utilization: Number of Slice Flip Flops: 69 out of 10,240 1% Number of 4 input LUTs: 1,138 out of 10,240 11% Logic Distribution: Number of occupied Slices: 736 out of 5,120 14% Number of Slices containing only related logic: 736 out of 736

100% Total Number 4 input LUTs: 1,427 out of 10,240 13% Number used as logic: 1,138 Number used as a route-thru: 33 Number used for Dual Port RAMs: 256 (Two LUTs used per Dual Port RAM)

Antti PS no need to ask any more "when do we see NI*S in Xilinx FPGA's" :)

Reply to
Antti Lukats
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So Antti, Can you answer the burning question: Does a Spartan-3 Nios-II beat a cyclone Microblaze in performance/area? How do the two compare?

This is really interesting work, and a great demonstration of the real differences between the architectures I think (i.e. putting a core specifically designed and optimized for one, into the other)

Reply to
Tails

the

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differences

benefit,

This is very nice and easy to do. I have a design using 2 NiosI/II's that divides the load and really increases performance. Nice to have as an easy option.

This may be true if you go the new HAL route, but I got my USB stack with fairly functional firmware into a 12KB onchip ram. (I used only standard C, linking etc.)

other

In my system NiosI varies from 3uS-11uS, but the NiosII is a rock solid 8uS. (NiosII varies by only +/- a few clocks each time) Not sure how good these numbers are compared to others.

to

is

Antti, maybe we should run the test suite from the UT Nios project on all these systems. That might be useful?

Ken

Reply to
Kenneth Land

Ok, I think I can answer the burning question :) answer is:

There is no significant differences at all !

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MicroBlaze, NIOS-II and also OR1K look very similar as of ISA

neither MicroBlaze or NIOS ISA is optimized or targetted for some specific FPGA fabric.

Sure MicroBlaze implementation is optimized for Xilinx primitives and NIOS for Altera primitives but that goes only for the implementation not for the CPU architecture per se. Same for NIOS-I its ISA is not in any optimized for ACEX and it would be working quite nicely in Cyclone too. But Altera has dropped NIOS-I.

The differences come from the SoC builder and Bus architecture, differences in bus mastering, IP cores used etc, not from the CPU architecture.

NIOS has simultaneous multimastering in some cases this could be a benefit, but only if really used properly.

Both MicroBlaze and NIOS being 32 bit CPU's are "memory hogs" smallest reasonable amount of code/data memory is 32KB (assuming thats the only memory available). With some care its possible to write real applications (like full OTG DRD Stack) that fit to 32KB, however in most cases external memory is required for code storage. So the speed of EMIF and caches are very important to speed up the execution from external memory.

Both MicroBlaze and NIOS are not very good in terms of interrupt latency unfortunatly :( at least when using default interrupt handler in C - hand coded assembly int handler could have smaller latency but could impose other problems.

NIOS bus peripherals are little easier to create then MicroBlaze OPB peripherals.

Both NIOS Custom Instruction and MicroBlaze FSL are "cool" solutions.

NIOS uCLinux is WAY easier to get started then MicroBlaze uCLinux thanks to the full integration of the config and integration into Eclipse workbench, as EDK6.3 is also Eclipse based it would be possible todo the same for MicroBlaze uClinux config and build.

hm.. I guess my answer was not a yes/no answer at all. Well there really is not any big differences - only matter of taste what FPGA what tools one chooses.

Antti

Reply to
Antti Lukats

What do you mean with

other

Could impose other problems??

I've written an interrupt handler that reënables the interrupts and is done fully in assmebler. Depending on the state of the Icache I reach 2 - 4µs. No one seems to reënable interrupts anymore (according to the altera documentation), but it can be done thay say.

But when I change the predefined niosII system from standard to the full featured one (with data cache). My system isn't stable anymore.

the

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benefit,

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Reply to
Vanheesbeke Stefaan

Well, I have been working on my own CPU. It runs at 88MHz in a Spartan

3 and 115MHz in a Cyclone II (fastest speed grade for both devices / post-layout timing). Given this is pretty much the same frequency (maybe a little faster :) ) as is achieved by MicroBlaze and NIOS II, I would say that they are very likely to achieve similar results if implemented in their competitors devices. This isn't really too much of a surprise given that both processors are quite similar.

Cheers, Jon

Reply to
Jon Beniston

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