hello guys, I am working on a verilog design. But the top level module is written in handel-C. First i synthesised the verilog design with the synthesis option 'Add I/O buffers' unchecked. it generated .ngc file. the synthesis report showed that the design used some 280 slices of the device considered.
Next while running NGDBUILD for the top level module, i used the ngc file generated, as it has to merge the two source files and create a single file. But while i am doing this i am getting several warnings as:
WARNING:NgdBuild:454 - logical net 'W168_send_protocol_56_main' has no load WARNING:NgdBuild:454 - logical net 'W169_send_protocol_56_main' has no load WARNING:NgdBuild:454 - logical net 'W170_send_protocol_56_main' has no load WARNING:NgdBuild:454 - logical net 'W171_send_protocol_56_main' has no load WARNING:NgdBuild:454 - logical net 'W172_send_protocol_56_main' has no load ...
send_protocol is the top level design name.
And the synthesis report shows that the design uses only 324 slices. i dont understand what the problem is. could anyone please help me.
thanks, kumar