Newcomer question

Hi there,

I am doing my first FPGA/VHDL design. Previously I did CPLD designs utilizing Altera's AHDL. I coded the VHDL source files and simulated it successfully with Modelsim. Then I made the I/O pin assignments and made the .bit file and loaded it to the FPGA. To my disappointment only some of the signals are correct; the functionality of the system does not work. I am using ispLEVER and a Lattice LFEC33 FPGA. There is a "Post Place and Route Simulation" action available within ispLEVER (actually it starts Modelsim), but this does not work. Modelsim always complains "Error loading design". What possibilities do I have to debug my design?

Thanks a lot,

Johannes

Reply to
Johannes Hausensteiner
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Hi,

For some reason my first post ended up in a complete different thread (XPower: Post-Place and Route Simulation model). Thanks to all of you answered there. Being (in my age still) impatient I sent this post a second time - I apologize for that.

Johannes

Johannes Hausenste> Hi there,

Reply to
Johannes Hausensteiner

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